/external/llvm/lib/Target/PowerPC/ |
PPCInstrBuilder.h | 11 // MachineInstrBuilder.h file to simplify generating frame and constant pool 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 32 static inline const MachineInstrBuilder& 33 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
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/external/llvm/include/llvm/CodeGen/ |
MachineInstrBuilder.h | 45 class MachineInstrBuilder { 49 MachineInstrBuilder() : MF(0), MI(0) {} 51 /// Create a MachineInstrBuilder for manipulating an existing instruction. 53 MachineInstrBuilder(MachineFunction &F, MachineInstr *I) : MF(&F), MI(I) {} 64 MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0, 83 const MachineInstrBuilder &addImm(int64_t Val) const { 88 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const { 93 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const { 98 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB, 104 const MachineInstrBuilder &addFrameIndex(int Idx) const [all...] |
/external/llvm/lib/Target/X86/ |
X86InstrBuilder.h | 11 // MachineInstrBuilder.h file to handle X86'isms in a clean way. 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 89 static inline const MachineInstrBuilder & 90 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) { 97 static inline const MachineInstrBuilder & 98 addOffset(const MachineInstrBuilder &MIB, int Offset) { 106 static inline const MachineInstrBuilder & 107 addRegOffset(const MachineInstrBuilder &MIB, 114 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.h | 25 class MachineInstrBuilder; 53 MachineInstrBuilder &MIB, 66 void AddRegisterOperand(MachineInstrBuilder &MIB, 77 void AddOperand(MachineInstrBuilder &MIB,
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InstrEmitter.cpp | 22 #include "llvm/CodeGen/MachineInstrBuilder.h" 207 MachineInstrBuilder &MIB, 295 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB, 357 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB, 540 MachineInstrBuilder MIB = 597 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg); 647 MachineInstrBuilder MIB = BuildMI(*MF, DL, II); 736 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II); [all...] |
/external/llvm/lib/Target/R600/ |
SIInstrInfo.h | 61 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 67 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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R600InstrInfo.h | 31 class MachineInstrBuilder; 136 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 141 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 156 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
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AMDGPUInstrInfo.h | 38 class MachineInstrBuilder; 176 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 184 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
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SIInstrInfo.cpp | 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 131 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL, 154 MachineInstrBuilder MIB(*MF, MI); 206 MachineInstrBuilder SIInstrInfo::buildIndirectWrite( 214 MachineInstrBuilder SIInstrInfo::buildIndirectRead(
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AMDGPUIndirectAddressing.cpp | 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 113 MachineInstrBuilder MOV = TII->buildIndirectWrite(BB, I, 187 MachineInstrBuilder Phi = BuildMI(MBB, MBB.begin(), 280 MachineInstrBuilder Sequence = BuildMI(MBB, I, MBB.findDebugLoc(I), 301 MachineInstrBuilder Mov = TII->buildIndirectRead(BB, I,
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R600InstrInfo.cpp | 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 78 MachineInstrBuilder MIB(*MF, MI); 515 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI); 610 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, 619 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, 626 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, 635 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, AMDGPU::MOV, 649 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB, 655 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
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/external/llvm/lib/Target/ARM/ |
ARMBaseInstrInfo.h | 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 320 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) { 325 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) { 330 const MachineInstrBuilder &AddDefaultT1CC(const MachineInstrBuilder &MIB, 336 const MachineInstrBuilder &AddNoT1CC(const MachineInstrBuilder &MIB) {
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ARMExpandPseudoInsts.cpp | 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 55 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 73 MachineInstrBuilder &UseMI, 74 MachineInstrBuilder &DefMI) { 383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 448 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 500 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 584 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 621 MachineInstrBuilder LO16, HI16 [all...] |
Thumb1FrameLowering.cpp | 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 318 MachineInstrBuilder MIB = 342 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(ARM::tPUSH)); 381 MachineInstrBuilder MIB = BuildMI(MF, DL, TII.get(ARM::tPOP));
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ARMInstrInfo.cpp | 23 #include "llvm/CodeGen/MachineInstrBuilder.h" 125 MachineInstrBuilder MIB = BuildMI(FirstMBB, MBBI, DL,
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Thumb1RegisterInfo.cpp | 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 130 MachineInstrBuilder MIB = 242 const MachineInstrBuilder MIB = 261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 269 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); 352 MachineInstrBuilder MIB(*MBB.getParent(), &MI); 563 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
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ARMBaseInstrInfo.cpp | 25 #include "llvm/CodeGen/MachineInstrBuilder.h" 467 MachineInstrBuilder(*MI->getParent()->getParent(), MI) 681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); 719 MachineInstrBuilder Mov; 751 MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, 798 MachineInstrBuilder MIB = 833 MachineInstrBuilder MIB = 854 MachineInstrBuilder MIB = 868 MachineInstrBuilder MIB [all...] |
ARMFastISel.cpp | 28 #include "llvm/CodeGen/MachineInstrBuilder.h" 224 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 226 const MachineInstrBuilder &MIB, 271 const MachineInstrBuilder & 272 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 672 MachineInstrBuilder MIB; 692 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 703 MachineInstrBuilder MIB; [all...] |
Thumb2ITBlockPass.cpp | 18 #include "llvm/CodeGen/MachineInstrBuilder.h" 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
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Thumb2SizeReduction.cpp | 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 467 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); 528 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), 691 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); 788 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); [all...] |
ARMFrameLowering.cpp | 21 #include "llvm/CodeGen/MachineInstrBuilder.h" 223 MachineInstrBuilder MIB = 447 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode)); 628 MachineInstrBuilder MIB = 634 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc), 693 MachineInstrBuilder MIB = 708 MachineInstrBuilder MIB = 791 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP) [all...] |
/external/llvm/lib/Target/Mips/ |
Mips16InstrInfo.cpp | 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 199 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 203 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 207 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::SwRxSpImmX16), 239 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 243 MachineInstrBuilder MIB0 = BuildMI(MBB, I, DL, get(Mips::Move32R16), 246 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 250 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::LwRxSpImmX16), 278 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1) [all...] |
MipsInstrInfo.cpp | 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 68 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Mips::DBG_VALUE)) 109 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
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/external/llvm/lib/CodeGen/ |
MachineSSAUpdater.cpp | 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 112 MachineInstrBuilder InsertNewDef(unsigned Opcode, 186 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB, 318 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
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/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 24 #include "llvm/CodeGen/MachineInstrBuilder.h" 123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE)) 312 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); 319 MachineInstrBuilder MIB = BuildMI(&MBB, DL, get(Cond[0].getImm())); 417 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(StoreOp)); 463 MachineInstrBuilder NewMI = BuildMI(MBB, MBBI, DL, get(LoadOp), DestReg);
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