| /external/llvm/include/llvm/Analysis/ |
| ConstantsScanner.h | 28 unsigned OpIdx; // Operand index
33 assert(!InstI.atEnd() && OpIdx < InstI->getNumOperands() &&
35 return isa<Constant>(InstI->getOperand(OpIdx));
39 inline constant_iterator(const Function *F) : InstI(inst_begin(F)), OpIdx(0) {
47 : InstI(inst_end(F)), OpIdx(0) {
50 inline bool operator==(const _Self& x) const { return OpIdx == x.OpIdx &&
56 return cast<Constant>(InstI->getOperand(OpIdx));
61 ++OpIdx;
64 while (OpIdx < NumOperands && !isAtConstant())
[all...] |
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCCodeEmitter.cpp | 80 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
83 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
89 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
94 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
98 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
102 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
106 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
111 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
116 uint32_t getUnconditionalBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
121 uint32_t getARMBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 41 unsigned getAddSubImmOpValue(const MCInst &MI, unsigned OpIdx,
44 unsigned getAdrpLabelOpValue(const MCInst &MI, unsigned OpIdx,
48 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
50 return getOffsetUImm12OpValue(MI, OpIdx, Fixups, MemSize);
53 unsigned getOffsetUImm12OpValue(const MCInst &MI, unsigned OpIdx,
57 unsigned getBitfield32LSLOpValue(const MCInst &MI, unsigned OpIdx,
59 unsigned getBitfield64LSLOpValue(const MCInst &MI, unsigned OpIdx,
66 unsigned getLabelOpValue(const MCInst &MI, unsigned OpIdx,
69 unsigned getLoadLitLabelOpValue(const MCInst &MI, unsigned OpIdx,
73 unsigned getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMCodeEmitter.cpp | 103 unsigned OpIdx);
156 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
157 return getMachineOpValue(MI, MI.getOperand(OpIdx));
251 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
253 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
293 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
295 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
297 uint32_t getPostIdxRegOpValue(const MachineInstr &MI, unsigned OpIdx)
299 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
376 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const
[all...] |
| ARMExpandPseudoInsts.cpp | 385 unsigned OpIdx = 0;
387 bool DstIsDead = MI.getOperand(OpIdx).isDead();
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
414 SrcOpIdx = OpIdx++;
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/utils/TableGen/ |
| CodeEmitterGen.cpp | 130 unsigned OpIdx;
131 if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
133 OpIdx = CGI.Operands[OpIdx].MIOperandNo;
134 assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
144 OpIdx = NumberedOp++;
147 std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
158 " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
165 " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
|
| CodeGenInstruction.cpp | 134 unsigned OpIdx;
135 if (hasOperandNamed(Name, OpIdx)) return OpIdx;
141 /// given name. If so, return true and set OpIdx to the index of the
143 bool CGIOperandList::hasOperandNamed(StringRef Name, unsigned &OpIdx) const {
147 OpIdx = i;
170 unsigned OpIdx = getOperandNamed(OpName);
174 if (OperandList[OpIdx].MINumOperands > 1 && !AllowWholeOp &&
180 return std::make_pair(OpIdx, 0U);
184 DagInit *MIOpInfo = OperandList[OpIdx].MIOperandInfo
[all...] |
| CodeGenInstruction.h | 159 /// given name. If so, return true and set OpIdx to the index of the
161 bool hasOperandNamed(StringRef Name, unsigned &OpIdx) const;
|
| /external/llvm/lib/CodeGen/ |
| MachineInstr.cpp | [all...] |
| MachineLICM.cpp | 247 unsigned Reg, unsigned OpIdx,
780 unsigned Reg, unsigned OpIdx,
[all...] |
| RegisterCoalescer.cpp | 658 unsigned OpIdx = NewMI->findRegisterUseOperandIdx(IntA.reg, false);
659 NewMI->getOperand(OpIdx).setIsKill();
[all...] |
| ScheduleDAGInstrs.cpp | 259 int UseOp = I->OpIdx;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 45 /// For non data-dependent uses, OpIdx == -1.
48 int OpIdx;
51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
|
| MachineInstr.h | [all...] |
| /external/llvm/lib/Target/R600/ |
| AMDGPUIndirectAddressing.cpp | 218 for (unsigned OpIdx = 0, NumOperands = MI.getNumOperands();
219 OpIdx < NumOperands; ++OpIdx) {
220 MachineOperand &MO = MI.getOperand(OpIdx);
|
| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 65 void EmitSrc(const MCInst &MI, unsigned OpIdx, raw_ostream &OS) const;
235 void R600MCCodeEmitter::EmitSrc(const MCInst &MI, unsigned OpIdx,
237 const MCOperand &MO = MI.getOperand(OpIdx);
272 if ((!(isFlagSet(MI, OpIdx, MO_FLAG_ABS)))
273 && (isFlagSet(MI, OpIdx, MO_FLAG_NEG) ||
282 if (isFlagSet(MI, OpIdx, MO_FLAG_ABS)) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGSDNodes.h | 103 unsigned OpIdx, SDep& dep) const;
|
| ScheduleDAGSDNodes.cpp | 620 unsigned OpIdx, SDep& dep) const{
628 unsigned DefIdx = Use->getOperand(OpIdx).getResNo();
631 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs();
632 int Latency = TII->getOperandLatency(InstrItins, Def, DefIdx, Use, OpIdx);
[all...] |
| LegalizeVectorTypes.cpp | [all...] |
| /external/llvm/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const {
52 return getMachineOpValue(MI, MI.getOperand(OpIdx));
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.h | 117 unsigned OpIdx, raw_ostream &O);
|
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 467 for (unsigned OpIdx = 0; OpIdx < 2; ++OpIdx) { // Visit operands.
468 Value *Op = I->getOperand(OpIdx);
507 I->setOperand(OpIdx, UndefValue::get(I->getType()));
[all...] |
| /external/llvm/include/llvm/Support/ |
| PatternMatch.h | 925 Argument_match(unsigned OpIdx, const Opnd_t &V) : OpI(OpIdx), Val(V) { }
|
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
