| /external/clang/test/CodeGen/ |
| mips-byval-arg.c | 6 } S0;
8 extern void foo2(S0);
13 void foo1(S0 a0) {
|
| mips64-padding-arg.c | 7 } S0;
9 // Insert padding to ensure arguments of type S0 are aligned to 16-byte boundaries.
15 extern void foo2(int, int, int, S0, S0, int, S0);
17 void foo1(int a0, S0 a1, S0 a2, int b, S0 a3) {
35 // N64: define void @foo5(%struct.S0* noalias sret %agg.result, i64, fp128 %a0)
36 // N64: call void @foo6(%struct.S0* sret %agg.result, i32 1, i32 2, i64 undef, fp128 %a0
[all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssemblerARM.cpp | 79 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
80 m_assembler.ldrh_u(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset));
81 m_assembler.ldrh_u(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(address.offset + 0x2));
83 m_assembler.add_r(ARMRegisters::S0, address.base, op2);
84 m_assembler.ldrh_d(dest, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset));
85 m_assembler.ldrh_d(ARMRegisters::S0, ARMRegisters::S0, ARMAssembler::getOp2Byte(-address.offset - 0x2));
87 m_assembler.ldr_un_imm(ARMRegisters::S0, address.offset);
88 m_assembler.add_r(ARMRegisters::S0, ARMRegisters::S0, op2)
[all...] |
| ARMAssembler.cpp | 272 add_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
273 dtr_u(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
275 moveImm(offset, ARMRegisters::S0);
276 dtr_ur(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
283 sub_r(ARMRegisters::S0, base, OP2_IMM | (offset >> 12) | (10 << 8));
284 dtr_d(isLoad, srcDst, ARMRegisters::S0, (offset & 0xfff) | transferFlag);
286 moveImm(offset, ARMRegisters::S0);
287 dtr_dr(isLoad, srcDst, base, ARMRegisters::S0 | transferFlag);
300 add_r(ARMRegisters::S0, base, op2);
301 dtr_u(isLoad, srcDst, ARMRegisters::S0, offset)
[all...] |
| MacroAssemblerARM.h | 98 m_assembler.adds_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
114 ARMWord w = m_assembler.getImm(imm.m_value, ARMRegisters::S0, true);
125 m_assembler.and_r(ARMRegisters::S0, shift_amount, w);
127 m_assembler.movs_r(dest, m_assembler.lsl_r(dest, ARMRegisters::S0));
138 move(src, ARMRegisters::S0);
139 src = ARMRegisters::S0;
146 move(imm, ARMRegisters::S0);
147 m_assembler.muls_r(dest, src, ARMRegisters::S0);
167 m_assembler.orrs_r(dest, dest, m_assembler.getImm(imm.m_value, ARMRegisters::S0));
174 m_assembler.and_r(ARMRegisters::S0, shift_amount, w)
[all...] |
| /external/clang/test/SemaCXX/ |
| type-definition-in-specifier.cpp | 3 struct S0;
11 struct S0 { int x; };
|
| /external/llvm/include/llvm/ADT/ |
| StringSwitch.h | 85 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
87 return Case(S0, Value).Case(S1, Value);
91 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
93 return Case(S0, Value).Case(S1, Value).Case(S2, Value);
97 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
100 return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value);
104 StringSwitch& Cases(const char (&S0)[N0], const char (&S1)[N1],
107 return Case(S0, Value).Case(S1, Value).Case(S2, Value).Case(S3, Value)
|
| /external/clang/test/ASTMerge/Inputs/ |
| struct1.c | 5 struct S0 {
10 struct S0 x0;
|
| struct2.c | 2 struct S0 {
7 struct S0 x0;
|
| /ndk/tests/device/test-stlport_shared-exception/jni/ |
| vtable2.cpp | 9 struct S0
11 virtual void s0 ();
14 struct S1 : virtual public S0
22 virtual void s0 ();
35 void S0::s0 () function in class:S0
47 void S2::s0 () function in class:S2
61 S0 primary vtable
63 S0 offset to top
64 S0 RTT
[all...] |
| /ndk/tests/device/test-stlport_static-exception/jni/ |
| vtable2.cpp | 9 struct S0
11 virtual void s0 ();
14 struct S1 : virtual public S0
22 virtual void s0 ();
35 void S0::s0 () function in class:S0
47 void S2::s0 () function in class:S2
61 S0 primary vtable
63 S0 offset to top
64 S0 RTT
[all...] |
| /external/llvm/unittests/ADT/ |
| VariadicFunctionTest.cpp | 71 std::string S0("hi");
72 EXPECT_EQ(0, StringAppend(&S0));
73 EXPECT_EQ("hi", S0);
|
| /external/clang/test/CXX/dcl.dcl/basic.namespace/namespace.def/namespace.memdef/ |
| p3.cpp | 10 struct S0 {
16 F0 f0() { return S0().member_func(); }
|
| /external/clang/test/CXX/temp/temp.arg/temp.arg.nontype/ |
| p5.cpp | 81 template <int& N> struct S0 { }; // expected-note 3 {{template parameter is declared here}}
90 S0<i> s0; local
91 S0<ci> s0c; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'const int' ignores qualifiers}}
92 S0<vi> s0v; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'volatile int' ignores qualifiers}}
93 S0<cvi> s0cv; // expected-error{{reference binding of non-type template parameter of type 'int &' to template argument of type 'const volatile int' ignores qualifiers}}
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_BitDec_s.h | 487 ;// $S0 - The number of bits to look up for the first step
488 ;// 1<=$S0<=8
490 ;// step 1<=$S1<=$S0.
506 M_BD_VLD $Symbol, $T1, $T2, $pVLDTable, $S0, $S1
507 ASSERT (1<=$S0):LAND:($S0<=8)
508 ASSERT (1<=$S1):LAND:($S1<=$S0)
513 MOVS $Symbol, #(2<<$S0)-2 ;// create mask
514 AND $Symbol, $Symbol, $T1, LSR #(31-$S0) ;// 2*(next $S0 bits
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_BitDec_s.h | 487 ;// $S0 - The number of bits to look up for the first step
488 ;// 1<=$S0<=8
490 ;// step 1<=$S1<=$S0.
506 M_BD_VLD $Symbol, $T1, $T2, $pVLDTable, $S0, $S1
507 ASSERT (1<=$S0):LAND:($S0<=8)
508 ASSERT (1<=$S1):LAND:($S1<=$S0)
513 MOVS $Symbol, #(2<<$S0)-2 ;// create mask
514 AND $Symbol, $Symbol, $T1, LSR #(31-$S0) ;// 2*(next $S0 bits
[all...] |
| /bionic/libc/arch-mips/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /development/ndk/platforms/android-9/arch-mips/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /external/llvm/lib/Target/Mips/ |
| Mips16FrameLowering.cpp | 65 SrcML = MachineLocation(Mips::S0);
73 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
92 .addReg(Mips::S0);
108 // Registers RA, S0,S1 are the callee saved registers and they
133 // Registers RA,S0,S1 are the callee saved registers and they will be restored
173 MF.getRegInfo().setPhysRegUsed(Mips::S0);
|
| MipsRegisterInfo.cpp | 136 Reserved.set(Mips::S0);
204 return TFI->hasFP(MF) ? Mips::S0 : Mips::SP;
|
| Mips16RegisterInfo.cpp | 106 FrameReg = Mips::S0;
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/machine/ |
| regnum.h | 52 #define S0 16
|
| /external/skia/bench/ |
| ScalarBench.cpp | 170 static SkBenchmark* S0(void* p) { return new FloatComparisonBench(p); }
175 static BenchRegistry gReg0(S0);
|
| /external/libgsm/src/ |
| long_term.c | 366 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
381 E = W * a; S0 += E; } else (a = lp[K])
407 if (S0 > L_max) { L_max = S0; Nc = lambda; }
532 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
547 E = W * a; S0 += E
573 if (S0 > L_max) { L_max = S0; Nc = lambda; }
746 register float S0 = 0, S1 = 0, S2 = 0, S3 = 0, S4 = 0,
761 E = W * a; S0 +=
[all...] |
