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Searched
refs:SRI
(Results
1 - 4
of
4
) sorted by null
/external/llvm/lib/MC/
MCRegisterInfo.cpp
31
const uint16_t *
SRI
= SubRegIndices + get(Reg).SubRegIndices;
32
for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++
SRI
)
33
if (*
SRI
== Idx)
42
const uint16_t *
SRI
= SubRegIndices + get(Reg).SubRegIndices;
43
for (MCSubRegIterator Subs(Reg, this); Subs.isValid(); ++Subs, ++
SRI
)
45
return *
SRI
;
/external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp
215
MCSuperRegIterator
SRI
(Reg, TRI);
216
assert(
SRI
.isValid() && "Expected a superreg");
217
unsigned SuperReg = *
SRI
;
218
++
SRI
;
219
assert(!
SRI
.isValid() && "Expected exactly one superreg");
/external/llvm/utils/TableGen/
CodeGenRegisters.cpp
266
SubRegMap::const_iterator
SRI
= Map.find(I->first);
267
if (
SRI
== Map.end())
269
// Add I->second as a name for the subreg
SRI
->second, assuming it is
271
if (SubRegs.count(I->second) || !Orphans.erase(
SRI
->second))
274
SubRegs.insert(std::make_pair(I->second,
SRI
->second));
[
all
...]
CodeGenSchedule.cpp
289
for (RecIter
SRI
= SRDefs.begin(), SRE = SRDefs.end();
SRI
!= SRE; ++
SRI
) {
290
assert(!getSchedRWIdx(*
SRI
, /*IsRead-*/true) && "duplicate SchedWrite");
291
SchedReads.push_back(CodeGenSchedRW(SchedReads.size(), *
SRI
));
[
all
...]
Completed in 175 milliseconds