/external/llvm/include/llvm/CodeGen/ |
ResourcePriorityQueue.h | 31 struct resource_sort : public std::binary_function<SUnit*, SUnit*, bool> { 35 bool operator()(const SUnit* left, const SUnit* right) const; 40 std::vector<SUnit> *SUnits; 49 std::vector<SUnit*> Queue; 71 std::vector<SUnit*> Packet; 86 void initNodes(std::vector<SUnit> &sunits); 88 void addNode(const SUnit *SU) { 92 void updateNode(const SUnit *SU) { [all...] |
LatencyPriorityQueue.h | 25 struct latency_sort : public std::binary_function<SUnit*, SUnit*, bool> { 29 bool operator()(const SUnit* left, const SUnit* right) const; 34 std::vector<SUnit> *SUnits; 43 std::vector<SUnit*> Queue; 52 void initNodes(std::vector<SUnit> &sunits) { 57 void addNode(const SUnit *SU) { 61 void updateNode(const SUnit *SU) { 80 virtual void push(SUnit *U) [all...] |
ScheduleHazardRecognizer.h | 20 class SUnit; 60 virtual HazardType getHazardType(SUnit *m, int Stalls = 0) { 71 virtual void EmitInstruction(SUnit *) {}
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ScheduleDAG.h | 28 class SUnit; 74 /// Dep - A pointer to the depending/depended-on SUnit, and an enum 76 PointerIntPair<SUnit *, 2, Kind> Dep; 106 SDep(SUnit *S, Kind kind, unsigned Reg) 125 SDep(SUnit *S, OrderKind kind) 178 //// getSUnit - Return the SUnit to which this edge points. 179 SUnit *getSUnit() const { 183 //// setSUnit - Assign the SUnit to which this edge points. 184 void setSUnit(SUnit *SU) { 267 /// SUnit - Scheduling unit. This is a node in the scheduling DAG [all...] |
ScheduleDAGInstrs.h | 32 /// An individual mapping from virtual register number to SUnit. 35 SUnit *SU; 37 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} 47 SUnit *SU; 51 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} 111 /// scheduling region is mapped to an SUnit. 112 DenseMap<MachineInstr*, SUnit*> MISUnitMap; 130 std::vector<SUnit *> PendingLoads; 152 /// \brief Resolve and cache a resolved scheduling class for an SUnit. 153 const MCSchedClassDesc *getSchedClass(SUnit *SU) const [all...] |
MachineScheduler.h | 121 virtual SUnit *pickNode(bool &IsTopNode) = 0; 128 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0; 132 virtual void releaseTopNode(SUnit *SU) = 0; 135 virtual void releaseBottomNode(SUnit *SU) = 0; 140 /// by an ID. SUnit::NodeQueueId is a mask of the ReadyQueues the SUnit is in. 147 std::vector<SUnit*> Queue; 157 bool isInQueue(SUnit *SU) const { return (SU->NodeQueueId & ID); } 165 typedef std::vector<SUnit*>::iterator iterator; 171 ArrayRef<SUnit*> elements() { return Queue; [all...] |
DFAPacketizer.h | 41 class SUnit; 107 std::map<MachineInstr*, SUnit*> MIToSUnit; 154 virtual bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) { 160 virtual bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) {
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ScoreboardHazardRecognizer.h | 28 class SUnit; 117 virtual HazardType getHazardType(SUnit *SU, int Stalls); 119 virtual void EmitInstruction(SUnit *SU);
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ScheduleDFS.h | 26 class SUnit; 73 /// \brief Per-SUnit data computed during DFS for various metrics. 104 /// DFS results for each SUnit in this DAG. 144 void compute(ArrayRef<SUnit> SUnits); 148 unsigned getNumInstrs(const SUnit *SU) const { 161 ILPValue getILP(const SUnit *SU) const { 172 unsigned getSubtreeID(const SUnit *SU) const {
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/external/llvm/lib/Target/R600/ |
R600MachineScheduler.h | 29 bool operator()(const SUnit *S1, const SUnit *S2) { 66 std::multiset<SUnit *, CompareSUnit> AvailableAlus[AluLast]; 95 virtual SUnit *pickNode(bool &IsTopNode); 96 virtual void schedNode(SUnit *SU, bool IsTopNode); 97 virtual void releaseTopNode(SUnit *SU); 98 virtual void releaseBottomNode(SUnit *SU); 103 int getInstKind(SUnit *SU); 105 AluKind getAluKind(SUnit *SU) const; 108 SUnit *AttemptFillSlot (unsigned Slot) [all...] |
R600MachineScheduler.cpp | 63 SUnit* R600SchedStrategy::pickNode(bool &IsTopNode) { 64 SUnit *SU = 0; 111 const SUnit &S = DAG->SUnits[i]; 121 void R600SchedStrategy::schedNode(SUnit *SU, bool IsTopNode) { 164 void R600SchedStrategy::releaseTopNode(SUnit *SU) { 173 void R600SchedStrategy::releaseBottomNode(SUnit *SU) { 185 R600SchedStrategy::AluKind R600SchedStrategy::getAluKind(SUnit *SU) const { 246 int R600SchedStrategy::getInstKind(SUnit* SU) { 290 SUnit *R600SchedStrategy::PopInst(std::multiset<SUnit *, CompareSUnit> &Q) [all...] |
/external/llvm/lib/CodeGen/ |
LatencyPriorityQueue.cpp | 22 bool latency_sort::operator()(const SUnit *LHS, const SUnit *RHS) const { 55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { 56 SUnit *OnlyAvailablePred = 0; 57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 59 SUnit &Pred = *I->getSUnit(); 72 void LatencyPriorityQueue::push(SUnit *SU) { 76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 91 void LatencyPriorityQueue::scheduledNode(SUnit *SU) [all...] |
ScheduleDAGPrinter.cpp | 44 static bool isNodeHidden(const SUnit *Node) { 48 static bool hasNodeAddressLabel(const SUnit *Node, 55 static std::string getEdgeAttributes(const SUnit *Node, 66 std::string getNodeLabel(const SUnit *Node, const ScheduleDAG *Graph); 67 static std::string getNodeAttributes(const SUnit *N, 79 std::string DOTGraphTraits<ScheduleDAG*>::getNodeLabel(const SUnit *SU,
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ScheduleDAG.cpp | 52 EntrySU = SUnit(); 53 ExitSU = SUnit(); 65 bool SUnit::addPred(const SDep &D, bool Required) { 76 SUnit *PredSU = I->getSUnit(); 95 SUnit *N = D.getSUnit(); 133 void SUnit::removePred(const SDep &D) { 141 SUnit *N = D.getSUnit(); 178 void SUnit::setDepthDirty() { 180 SmallVector<SUnit*, 8> WorkList; 183 SUnit *SU = WorkList.pop_back_val() [all...] |
ScheduleDAGInstrs.cpp | 241 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { 253 SUnit *UseSU = I->SU; 282 /// this SUnit to following instructions in the same scheduling region that 284 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { 300 SUnit *DefSU = I->SU; 323 // Push this SUnit on the use list. 358 /// addVRegDefDeps - Add register output and data dependencies from this SUnit 364 void ScheduleDAGInstrs::addVRegDefDeps(SUnit *SU, unsigned OperIdx) { 385 SUnit *DefSU = DefI->SU; 399 /// defines the virtual register used at OperIdx is mapped to an SUnit. Add [all...] |
/external/llvm/include/llvm/Target/ |
TargetSubtargetInfo.h | 25 class SUnit; 75 virtual void adjustSchedDependency(SUnit *def, SUnit *use,
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/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.h | 30 /// nodes into a single SUnit so that they are scheduled together. 42 /// The schedule. Null SUnit*'s represent noop instructions. 43 std::vector<SUnit*> Sequence; 73 /// NewSUnit - Creates a new SUnit and return a ptr to it. 75 SUnit *newSUnit(SDNode *N); 77 /// Clone - Creates a clone of the specified SUnit. It does not copy the 80 SUnit *Clone(SUnit *N); 82 /// BuildSchedGraph - Build the SUnit graph from the selection dag that we 83 /// are input. This SUnit graph is similar to the SelectionDAG, bu [all...] |
ScheduleDAGVLIW.cpp | 60 std::vector<SUnit*> PendingQueue; 86 void releaseSucc(SUnit *SU, const SDep &D); 87 void releaseSuccessors(SUnit *SU); 88 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle); 115 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { 116 SUnit *SuccSU = D.getSUnit(); 139 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { 141 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 153 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { 185 std::vector<SUnit*> NotReady [all...] |
ResourcePriorityQueue.cpp | 71 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { 73 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 78 SUnit *PredSU = I->getSUnit(); 108 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, 111 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 116 SUnit *SuccSU = I->getSUnit(); 146 static unsigned numberCtrlDepsInSU(SUnit *SU) { 148 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); 156 static unsigned numberCtrlPredInSU(SUnit *SU) { 158 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end() [all...] |
ScheduleDAGFast.cpp | 48 SmallVector<SUnit *, 16> Queue; 52 void push(SUnit *U) { 56 SUnit *pop() { 58 SUnit *V = Queue.back(); 76 std::vector<SUnit*> LiveRegDefs; 85 /// AddPred - adds a predecessor edge to SUnit SU. 87 void AddPred(SUnit *SU, const SDep &D) { 91 /// RemovePred - removes a predecessor edge from SUnit SU. 93 void RemovePred(SUnit *SU, const SDep &D) { 98 void ReleasePred(SUnit *SU, SDep *PredEdge) [all...] |
ScheduleDAGRRList.cpp | 124 std::vector<SUnit*> PendingQueue; 143 std::vector<SUnit*> LiveRegDefs; 144 std::vector<SUnit*> LiveRegGens; 147 // Each interference is an SUnit and set of physical registers. 148 SmallVector<SUnit*, 4> Interferences; 149 typedef DenseMap<SUnit*, SmallVector<unsigned, 4> > LRegsMapT; 158 DenseMap<SUnit*, SUnit*> CallSeqEndForStart; 185 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.h | 52 std::vector<SUnit*> Packet; 88 bool isResourceAvailable(SUnit *SU); 89 bool reserveResources(SUnit *SU); 114 // The best SUnit candidate. 115 SUnit *SU; 176 bool checkHazard(SUnit *SU); 178 void releaseNode(SUnit *SU, unsigned ReadyCycle); 182 void bumpNode(SUnit *SU); 186 void removeReady(SUnit *SU); 188 SUnit *pickOnlyChoice() [all...] |
HexagonMachineScheduler.cpp | 25 SUnit* LastSequentialCall = NULL; 43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { 68 for (SUnit::const_succ_iterator I = Packet[i]->Succs.begin(), 83 bool VLIWResourceModel::reserveResources(SUnit *SU) { 156 SmallVector<SUnit*, 8> TopRoots, BotRoots; 164 // FIXME: SUnit::dumpAll always recompute depth and height now. The max 182 while (SUnit *SU = SchedImpl->pickNode(IsTopNode)) { 219 void ConvergingVLIWScheduler::releaseTopNode(SUnit *SU) { 223 for (SUnit::succ_iterator I = SU->Preds.begin(), E = SU->Preds.end(); 236 void ConvergingVLIWScheduler::releaseBottomNode(SUnit *SU) [all...] |
/external/llvm/lib/Target/PowerPC/ |
PPCHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls); 34 virtual void EmitInstruction(SUnit *SU); 68 virtual HazardType getHazardType(SUnit *SU, int Stalls); 69 virtual void EmitInstruction(SUnit *SU);
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/external/llvm/lib/Target/ARM/ |
ARMHazardRecognizer.h | 47 virtual HazardType getHazardType(SUnit *SU, int Stalls); 49 virtual void EmitInstruction(SUnit *SU);
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