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Searched
refs:SuperReg
(Results
1 - 5
of
5
) sorted by null
/external/llvm/lib/Target/Hexagon/
HexagonFrameLowering.cpp
216
assert(SRI.isValid() && "Expected a
superreg
");
217
unsigned
SuperReg
= *SRI;
219
assert(!SRI.isValid() && "Expected exactly one
superreg
");
220
return
SuperReg
;
249
unsigned
SuperReg
= uniqueSuperReg(Reg, TRI);
255
SuperRegClass = TRI->getMinimalPhysRegClass(
SuperReg
);
256
CanUseDblStore = (SuperRegNext ==
SuperReg
);
261
TII.storeRegToStackSlot(MBB, MI,
SuperReg
, true,
263
MBB.addLiveIn(
SuperReg
);
304
unsigned
SuperReg
= uniqueSuperReg(Reg, TRI)
[
all
...]
/external/llvm/lib/CodeGen/
AggressiveAntiDepBreaker.cpp
549
unsigned
SuperReg
= 0;
552
if ((
SuperReg
== 0) || TRI->isSuperRegister(
SuperReg
, Reg))
553
SuperReg
= Reg;
569
// All group registers should be a subreg of
SuperReg
.
572
if (Reg ==
SuperReg
) continue;
573
bool IsSub = TRI->isSubRegister(
SuperReg
, Reg);
586
dbgs() << "*** Performing rename " << TRI->getName(
SuperReg
) <<
591
// Check each possible rename register for
SuperReg
in round-robin
600
TRI->getMinimalPhysRegClass(
SuperReg
, MVT::Other)
[
all
...]
PostRASchedulerList.cpp
453
const unsigned
SuperReg
= MO.getReg();
455
for (MCSubRegIterator SubRegs(
SuperReg
, TRI); SubRegs.isValid(); ++SubRegs) {
/external/llvm/lib/Target/ARM/
ARMISelDAGToDAG.cpp
[
all
...]
/external/llvm/lib/Target/R600/
R600InstrInfo.cpp
584
unsigned
SuperReg
= AMDGPU::R600_Reg128RegClass.getRegister(Index);
585
Regs.push_back(
SuperReg
);
Completed in 441 milliseconds