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  /external/oprofile/events/mips/25K/
events 35 event:0x11 counters:0,1 um:zero minimum:500 name:UTLB_MISSES : U-TLB misses
36 event:0x12 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_IFETCH : Raw count of Joint-TLB misses for instruction fetch
37 event:0x13 counters:0,1 um:zero minimum:500 name:JTLB_MISSES_LOADS_STORES : Raw count of Joint-TLB misses for loads/stores
38 event:0x14 counters:0,1 um:zero minimum:500 name:JTLB_EXCEPTIONS : Refill, Invalid and Modified TLB exceptions
43 event:0x15 counters:0,1 um:zero minimum:500 name:JTLB_IFETCH_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to instruction fetch
44 event:0x16 counters:0,1 um:zero minimum:500 name:JTLB_DATA_ACCESS_REFILL_EXCEPTIONS : Joint-TLB refill exceptions due to data access
45 event:0x17 counters:0,1 um:zero minimum:500 name:JTLB_REFILL_EXCEPTIONS : total Joint-TLB Instruction exceptions (refill)
  /external/oprofile/events/mips/rm7000/
events 17 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
18 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
19 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
20 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
  /external/oprofile/events/mips/rm9000/
events 16 event:0x0d counters:0,1 um:zero minimum:500 name:DTLB_MISSES : Data TLB misses
17 event:0x0e counters:0,1 um:zero minimum:500 name:ITLB_MISSES : Instruction TLB misses
18 event:0x0f counters:0,1 um:zero minimum:500 name:JTLB_INSTRUCTION_MISSES : Joint TLB instruction misses
19 event:0x10 counters:0,1 um:zero minimum:500 name:JTLB_DATA_MISSES : Joint TLB data misses
  /external/clang/lib/Sema/
TreeTransform.h 303 QualType TransformType(TypeLocBuilder &TLB, TypeLoc TL);
528 QualType Transform##CLASS##Type(TypeLocBuilder &TLB, CLASS##TypeLoc T);
531 QualType TransformFunctionProtoType(TypeLocBuilder &TLB,
540 TransformTemplateSpecializationType(TypeLocBuilder &TLB,
545 TransformDependentTemplateSpecializationType(TypeLocBuilder &TLB,
551 TransformDependentTemplateSpecializationType(TypeLocBuilder &TLB,
578 QualType TransformReferenceType(TypeLocBuilder &TLB, ReferenceTypeLoc TL);
    [all...]
SemaCXXScopeSpec.cpp 594 TypeLocBuilder TLB;
597 = TLB.push<InjectedClassNameTypeLoc>(T);
600 RecordTypeLoc RecordTL = TLB.push<RecordTypeLoc>(T);
603 TypedefTypeLoc TypedefTL = TLB.push<TypedefTypeLoc>(T);
606 EnumTypeLoc EnumTL = TLB.push<EnumTypeLoc>(T);
610 = TLB.push<TemplateTypeParmTypeLoc>(T);
614 = TLB.push<UnresolvedUsingTypeLoc>(T);
618 = TLB.push<SubstTemplateTypeParmTypeLoc>(T);
622 = TLB.push<SubstTemplateTypeParmPackTypeLoc>(T);
631 SS.Extend(Context, SourceLocation(), TLB.getTypeLocInContext(Context, T)
    [all...]
SemaTemplateInstantiate.cpp     [all...]
SemaTemplate.cpp     [all...]
SemaTemplateDeduction.cpp     [all...]
  /external/oprofile/events/mips/20K/
events 10 event:0x4 counters:0 um:zero minimum:500 name:TLB_REFILLS_TAKEN : Taken TLB refill exceptions
13 event:0x7 counters:0 um:zero minimum:500 name:JTLB_EXCEPTIONS : Taken Joint-TLB exceptions
  /external/oprofile/events/mips/vr5500/
events 13 event:0x7 counters:0,1 um:zero minimum:500 name:JTLB_REFILLS : TLB refill
  /external/oprofile/events/mips/24K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
89 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
90 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
91 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
92 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
  /external/oprofile/events/mips/34K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
96 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
97 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
98 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
99 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
  /external/oprofile/events/x86-64/family10/
unit_masks 122 0x04 TLB fill (page table walks)
129 0x04 TLB page table walk
132 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
194 0x01 L2 4K TLB hit
195 0x02 L2 2M TLB hit
196 0x04 L2 1G TLB hit (RevC)
198 0x01 4K TLB reload
199 0x02 2M TLB reload
200 0x04 1G TLB reload
276 0x01 L1 4K TLB hi
    [all...]
  /external/oprofile/events/mips/1004K/
events 24 event:0x5 counters:0 um:zero minimum:500 name:ITLB_ACCESSES : 5-0 Instruction micro-TLB accesses
25 event:0x6 counters:0 um:zero minimum:500 name:DTLB_ACCESSES : 6-0 Data micro-TLB accesses
26 event:0x7 counters:0 um:zero minimum:500 name:JTLB_INSN_ACCESSES : 7-0 Joint TLB instruction accesses
27 event:0x8 counters:0 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 8-0 Joint TLB data (non-instruction) accesses
104 event:0x405 counters:1 um:zero minimum:500 name:ITLB_MISSES : 5-1 Instruction micro-TLB misses
105 event:0x406 counters:1 um:zero minimum:500 name:DTLB_MISSES : 6-1 Data micro-TLB misses
106 event:0x407 counters:1 um:zero minimum:500 name:JTLB_INSN_MISSES : 7-1 Joint TLB instruction misses
107 event:0x408 counters:1 um:zero minimum:500 name:JTLB_DATA_MISSES : 8-1 Joint TLB data (non-instruction) misses
  /external/openssl/crypto/bn/asm/
sparcv9a-mont.pl 152 and %o0,-2048,%o0 ! optimize TLB utilization
ppc64-mont.pl 215 and $tp,$tp,$i ; minimize TLB usage
ppc-mont.pl 129 and $ovf,$ovf,$tj ; minimize TLB usage
  /external/oprofile/events/mips/5K/
events 32 event:0x7 counters:1 um:zero minimum:500 name:TLB_MISS_EXCEPTIONS : TLB miss exceptions
  /external/oprofile/events/x86-64/family11h/
unit_masks 116 0x04 TLB fill (page table walk)
122 0x04 TLB page table walk
124 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
  /external/oprofile/events/x86-64/hammer/
unit_masks 105 0x04 TLB fill (page table walk)
111 0x04 TLB page table walk
113 0x01 L2 fills (victims from L1 caches, TLB page table walks and data prefetches)
  /external/oprofile/events/mips/r10000/
events 20 event:0x07 counters:1 um:zero minimum:500 name:TLB_REFILL_EXCEPTIONS : TLB refill exceptions
  /external/oprofile/events/mips/r12000/
events 27 event:0x17 counters:0,1,2,3 um:zero minimum:500 name:TLB_MISSES : TLB misses
  /external/kernel-headers/original/asm-arm/
tlbflush.h 16 #define tlb_flush(tlb) ((void) tlb)
46 * MMU TLB Model
52 * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
53 * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
54 * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
142 #error Unknown TLB model
176 * TLB Management
179 * The arch/arm/mm/tlb-*.S files implement these methods.
181 * The TLB specific code is expected to perform whatever tests i
    [all...]
  /external/oprofile/events/mips/74K/
events 22 event:0x4 counters:0,2 um:zero minimum:500 name:ITLB_ACCESSES : 4-0 Instruction micro-TLB accesses
43 event:0x19 counters:0,2 um:zero minimum:500 name:JTLB_DATA_ACCESSES : 25-0 Joint TLB data (non-instruction) accesses
98 event:0x404 counters:1,3 um:zero minimum:500 name:ITLB_MISSES : 4-1 Instruction micro-TLB misses
99 event:0x405 counters:1,3 um:zero minimum:500 name:JTLB_INSN_MISSES : 5-1 Joint TLB instruction misses
119 event:0x419 counters:1,3 um:zero minimum:500 name:JTLB_DATA_MISSES : 25-1 Joint TLB data (non-instruction) misses
  /external/oprofile/events/i386/nehalem/
events 27 event:0x0C counters:0,1,2,3 um:mem_store_retired minimum:6000 name:MEM_STORE_RETIRED : The event counts the number of retired stores that missed the DTLB. The DTLB miss is not counted if the store operation causes a fault. Does not count prefetches. Counts both primary and secondary misses to the TLB
55 event:0x4F counters:0,1,2,3 um:ept minimum:6000 name:EPT : Counts Extended Page Directory Entry accesses. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.

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