| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 24 namespace TargetOpcode {
96 } // end namespace TargetOpcode
|
| TargetInstrInfo.h | 70 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstr.h | 629 return getOpcode() == TargetOpcode::PROLOG_LABEL ||
630 getOpcode() == TargetOpcode::EH_LABEL ||
631 getOpcode() == TargetOpcode::GC_LABEL;
635 return getOpcode() == TargetOpcode::PROLOG_LABEL;
637 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
638 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
639 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
641 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
642 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
643 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF;
[all...] |
| /external/llvm/lib/CodeGen/ |
| ExpandPostRAPseudos.cpp | 101 MI->setDesc(TII->get(TargetOpcode::KILL));
112 MI->setDesc(TII->get(TargetOpcode::KILL));
139 MI->setDesc(TII->get(TargetOpcode::KILL));
154 MI->setDesc(TII->get(TargetOpcode::KILL));
209 case TargetOpcode::SUBREG_TO_REG:
212 case TargetOpcode::COPY:
215 case TargetOpcode::DBG_VALUE:
217 case TargetOpcode::INSERT_SUBREG:
218 case TargetOpcode::EXTRACT_SUBREG:
|
| StackColoring.cpp | 258 if (BI->getOpcode() != TargetOpcode::LIFETIME_START &&
259 BI->getOpcode() != TargetOpcode::LIFETIME_END)
264 bool IsStart = BI->getOpcode() == TargetOpcode::LIFETIME_START;
410 assert((MI->getOpcode() == TargetOpcode::LIFETIME_START ||
411 MI->getOpcode() == TargetOpcode::LIFETIME_END) &&
414 bool IsStart = MI->getOpcode() == TargetOpcode::LIFETIME_START;
517 if (I->getOpcode() == TargetOpcode::LIFETIME_START ||
518 I->getOpcode() == TargetOpcode::LIFETIME_END)
602 if (I->getOpcode() == TargetOpcode::LIFETIME_START ||
603 I->getOpcode() == TargetOpcode::LIFETIME_END || I->isDebugValue()
[all...] |
| MachineSSAUpdater.cpp | 149 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
186 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB,
296 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF,
308 MachineInstr *PHI = InsertNewDef(TargetOpcode::PHI, BB, Loc,
|
| PHIElimination.cpp | 244 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg);
260 TII->get(TargetOpcode::COPY), DestReg)
384 TII->get(TargetOpcode::IMPLICIT_DEF),
393 TII->get(TargetOpcode::COPY), IncomingReg)
|
| ProcessImplicitDefs.cpp | 92 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF));
|
| PeepholeOptimizer.cpp | 226 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
285 TII->get(TargetOpcode::COPY), NewVR)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 53 case TargetOpcode::EXTRACT_SUBREG:
54 case TargetOpcode::INSERT_SUBREG:
55 case TargetOpcode::SUBREG_TO_REG:
56 case TargetOpcode::REG_SEQUENCE:
57 case TargetOpcode::IMPLICIT_DEF:
58 case TargetOpcode::COPY:
59 case TargetOpcode::INLINEASM:
105 case TargetOpcode::EXTRACT_SUBREG:
106 case TargetOpcode::INSERT_SUBREG:
107 case TargetOpcode::SUBREG_TO_REG
[all...] |
| HexagonNewValueJump.cpp | 111 if (II->getOpcode() == TargetOpcode::KILL)
175 if (MII->getOpcode() == TargetOpcode::KILL ||
176 MII->getOpcode() == TargetOpcode::PHI ||
177 MII->getOpcode() == TargetOpcode::COPY)
235 if (def->getOpcode() == TargetOpcode::COPY)
|
| HexagonAsmPrinter.cpp | 209 if (MInst->getOpcode() == TargetOpcode::DBG_VALUE ||
210 MInst->getOpcode() == TargetOpcode::IMPLICIT_DEF) {
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 176 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF &&
270 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) {
281 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
323 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
443 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
471 if (Opc == TargetOpcode::EXTRACT_SUBREG) {
493 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
509 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx);
511 } else if (Opc == TargetOpcode::INSERT_SUBREG |
[all...] |
| ResourcePriorityQueue.cpp | 264 case TargetOpcode::EXTRACT_SUBREG:
265 case TargetOpcode::INSERT_SUBREG:
266 case TargetOpcode::SUBREG_TO_REG:
267 case TargetOpcode::REG_SEQUENCE:
268 case TargetOpcode::IMPLICIT_DEF:
304 case TargetOpcode::EXTRACT_SUBREG:
305 case TargetOpcode::INSERT_SUBREG:
306 case TargetOpcode::SUBREG_TO_REG:
307 case TargetOpcode::REG_SEQUENCE:
308 case TargetOpcode::IMPLICIT_DEF
[all...] |
| FastISel.cpp | 83 while (I != E && I->getOpcode() == TargetOpcode::EH_LABEL) {
237 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
324 FuncInfo.InsertPt->getOpcode() == TargetOpcode::EH_LABEL)
580 TII.get(TargetOpcode::INLINEASM))
645 TII.get(TargetOpcode::DBG_VALUE))
657 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY),
[all...] |
| ScheduleDAGRRList.cpp | 297 if (Opcode == TargetOpcode::REG_SEQUENCE) {
[all...] |
| ScheduleDAGSDNodes.cpp | 82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF))
539 if (POpc == TargetOpcode::IMPLICIT_DEF) {
778 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
787 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430InstrInfo.cpp | 299 case TargetOpcode::PROLOG_LABEL:
300 case TargetOpcode::EH_LABEL:
301 case TargetOpcode::IMPLICIT_DEF:
302 case TargetOpcode::KILL:
303 case TargetOpcode::DBG_VALUE:
305 case TargetOpcode::INLINEASM: {
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCCodeEmitter.cpp | 121 case TargetOpcode::PROLOG_LABEL:
122 case TargetOpcode::EH_LABEL:
125 case TargetOpcode::IMPLICIT_DEF:
126 case TargetOpcode::KILL:
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 500 case TargetOpcode::DBG_VALUE:
577 case TargetOpcode::BUNDLE:
579 case TargetOpcode::IMPLICIT_DEF:
580 case TargetOpcode::KILL:
581 case TargetOpcode::PROLOG_LABEL:
582 case TargetOpcode::EH_LABEL:
583 case TargetOpcode::DBG_VALUE:
776 TII->get(TargetOpcode::COPY),
801 TII->get(TargetOpcode::COPY),
|
| AArch64FrameLowering.cpp | 96 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
132 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
163 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
177 BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::PROLOG_LABEL))
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 74 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
91 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
135 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel2);
152 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(SetFPLabel);
|
| Mips16FrameLowering.cpp | 52 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
59 TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
|
| MipsInstrInfo.cpp | 278 case TargetOpcode::INLINEASM: { // Inline Asm: Variable size.
|
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 459 TII->get(TargetOpcode::COPY), Out)
475 TII->get(TargetOpcode::REG_SEQUENCE), Out)
510 TII->get(TargetOpcode::INSERT_SUBREG), Out)
526 TII->get(TargetOpcode::IMPLICIT_DEF), Out);
|
