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    Searched refs:TargetRegisterClass (Results 1 - 25 of 172) sorted by null

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  /external/llvm/lib/Target/R600/
R600RegisterInfo.h 37 virtual const TargetRegisterClass *getISARegClass(
38 const TargetRegisterClass *RC) const;
45 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
SIRegisterInfo.h 37 virtual const TargetRegisterClass *
38 getISARegClass(const TargetRegisterClass *RC) const;
42 virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
AMDGPURegisterInfo.h 45 virtual const TargetRegisterClass * getISARegClass(
46 const TargetRegisterClass * RC) const {
50 virtual const TargetRegisterClass* getCFGStructurizerRegClass(MVT VT) const {
SIRegisterInfo.cpp 33 const TargetRegisterClass *
34 SIRegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
42 const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass(
SIInstrInfo.h 47 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
56 virtual const TargetRegisterClass *getIndirectAddrStoreRegClass(
59 virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const;
73 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
R600RegisterInfo.cpp 47 for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(),
52 for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(),
68 const TargetRegisterClass *
69 R600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const {
82 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
  /external/llvm/lib/Target/X86/
X86RegisterInfo.h 75 virtual const TargetRegisterClass *
76 getMatchingSuperRegClass(const TargetRegisterClass *A,
77 const TargetRegisterClass *B, unsigned Idx) const;
79 virtual const TargetRegisterClass *
80 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
82 const TargetRegisterClass*
83 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
85 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
87 const TargetRegisterClass *
93 const TargetRegisterClass *
    [all...]
  /external/llvm/include/llvm/CodeGen/
RegisterClassInfo.h 66 void compute(const TargetRegisterClass *RC) const;
69 const RCInfo &get(const TargetRegisterClass *RC) const {
85 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
92 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
102 bool isProperSubClass(const TargetRegisterClass *RC) const {
118 unsigned getMinCost(const TargetRegisterClass *RC) {
126 unsigned getLastCostChange(const TargetRegisterClass *RC) {
RegisterScavenging.h 29 class TargetRegisterClass;
53 const TargetRegisterClass *ScavengedRC;
104 BitVector getRegsAvailable(const TargetRegisterClass *RC);
108 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
119 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
121 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) {
FastISel.h 40 class TargetRegisterClass;
260 const TargetRegisterClass *RC);
266 const TargetRegisterClass *RC,
273 const TargetRegisterClass *RC,
281 const TargetRegisterClass *RC,
290 const TargetRegisterClass *RC,
298 const TargetRegisterClass *RC,
306 const TargetRegisterClass *RC,
314 const TargetRegisterClass *RC,
323 const TargetRegisterClass *RC
    [all...]
MachineSSAUpdater.h 26 class TargetRegisterClass;
48 const TargetRegisterClass *VRC;
LiveStackAnalysis.h 40 std::map<int, const TargetRegisterClass*> S2RCMap;
57 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
77 const TargetRegisterClass *getIntervalRegClass(int Slot) const {
79 std::map<int, const TargetRegisterClass*>::const_iterator
  /external/llvm/lib/Target/Mips/
MipsMachineFunction.cpp 36 const TargetRegisterClass *RC;
38 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
41 (const TargetRegisterClass*)&Mips::CPU64RegsRegClass :
42 (const TargetRegisterClass*)&Mips::CPURegsRegClass;
54 const TargetRegisterClass *RC;
55 RC=(const TargetRegisterClass*)&Mips::CPU16RegsRegClass;
62 const TargetRegisterClass *RC = ST.isABI_N64() ?
  /external/llvm/include/llvm/Target/
TargetRegisterInfo.h 36 class TargetRegisterClass {
41 typedef const TargetRegisterClass* const * sc_iterator;
102 /// hasType - return true if this TargetRegisterClass has the ValueType vt.
123 /// hasSubClass - return true if the specified TargetRegisterClass
124 /// is a proper sub-class of this TargetRegisterClass.
125 bool hasSubClass(const TargetRegisterClass *RC) const {
131 bool hasSubClassEq(const TargetRegisterClass *RC) const {
136 /// hasSuperClass - return true if the specified TargetRegisterClass is a
137 /// proper super-class of this TargetRegisterClass.
138 bool hasSuperClass(const TargetRegisterClass *RC) const
    [all...]
TargetSubtargetInfo.h 26 class TargetRegisterClass;
45 typedef SmallVectorImpl<const TargetRegisterClass*> RegClassVector;
  /external/llvm/lib/Target/AArch64/
AArch64RegisterInfo.h 50 const TargetRegisterClass *
51 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
55 const TargetRegisterClass*
56 getLargestLegalSuperClass(const TargetRegisterClass *RC) const {
  /external/llvm/lib/Target/ARM/
Thumb1RegisterInfo.h 30 const TargetRegisterClass*
31 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
33 const TargetRegisterClass*
57 const TargetRegisterClass *RC,
Thumb1InstrInfo.h 49 const TargetRegisterClass *RC,
55 const TargetRegisterClass *RC,
ARMBaseRegisterInfo.h 103 const TargetRegisterClass*
105 const TargetRegisterClass*
106 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
108 const TargetRegisterClass*
109 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
111 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
123 virtual bool avoidWriteAfterWrite(const TargetRegisterClass *RC) const;
Thumb2InstrInfo.h 51 const TargetRegisterClass *RC,
57 const TargetRegisterClass *RC,
  /external/llvm/lib/CodeGen/
TargetRegisterInfo.cpp 76 const TargetRegisterClass *
77 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
87 const TargetRegisterClass *SubRC = getRegClass(Idx + Offset);
100 const TargetRegisterClass *
106 const TargetRegisterClass* BestRC = 0;
108 const TargetRegisterClass* RC = *I;
121 const TargetRegisterClass *RC, BitVector &R){
129 const TargetRegisterClass *RC) const {
133 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
151 const TargetRegisterClass *firstCommonClass(const uint32_t *A
    [all...]
RegisterCoalescer.h 22 class TargetRegisterClass;
59 const TargetRegisterClass *NewRC;
116 const TargetRegisterClass *getNewRC() const { return NewRC; }
LiveStackAnalysis.cpp 58 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
67 const TargetRegisterClass *OldRC = S2RCMap[Slot];
80 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
  /external/llvm/lib/Target/NVPTX/
NVPTXRegisterInfo.h 52 virtual const TargetRegisterClass* const *
78 std::string getNVPTXRegClassName (const TargetRegisterClass *RC);
79 std::string getNVPTXRegClassStr (const TargetRegisterClass *RC);
NVPTXRegisterInfo.cpp 31 std::string getNVPTXRegClassName (TargetRegisterClass const *RC) {
63 std::string getNVPTXRegClassStr (TargetRegisterClass const *RC) {
111 const TargetRegisterClass* const*
113 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };

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