| /external/llvm/utils/TableGen/ |
| AsmWriterInst.cpp | 128 CGI.TheDef->getName() + "'!");
167 + CGI.TheDef->getName() + "'");
174 + CGI.TheDef->getName() + "'");
182 PrintFatalError("Bad operand modifier name in '"+ CGI.TheDef->getName() + "'");
187 + CGI.TheDef->getName() + "'");
191 PrintFatalError("Stray '$' in '" + CGI.TheDef->getName() +
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| CodeGenIntrinsics.h | 27 Record *TheDef; // The actual record defining this intrinsic.
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| InstrInfoEmitter.cpp | 206 Record *Inst = (*II)->TheDef;
239 InstrNames.add(Instr->TheDef->getName());
252 OS << InstrNames.get(Instr->TheDef->getName()) << "U, ";
313 << Inst.TheDef->getValueAsInt("Size") << ",\t0";
346 BitsInit *TSF = Inst.TheDef->getValueAsBitsInit("TSFlags");
354 PrintFatalError("Invalid TSFlags bit in " + Inst.TheDef->getName());
361 std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
367 std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
380 OS << " }, // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
407 OS << " " << NumberedInstructions[i]->TheDef->getName(
[all...] |
| CodeGenSchedule.h | 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
49 Record *TheDef;
59 : Index(0), TheDef(0), IsRead(false), IsAlias(false),
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
77 : Index(Idx), Name(Name), TheDef(0), IsRead(Read), IsAlias(false),
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
88 return TheDef || !Sequence.empty();
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| AsmMatcherEmitter.cpp | 393 /// TheDef - This is the definition of the instruction or InstAlias that this
395 Record *const TheDef;
433 : AsmVariantID(0), TheDef(CGI.TheDef), DefRec(&CGI),
438 : AsmVariantID(0), TheDef(Alias->TheDef), DefRec(Alias),
561 Record *TheDef;
566 SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {}
570 return "Feature_" + TheDef->getName();
678 errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"
[all...] |
| CodeGenInstruction.cpp | 28 CGIOperandList::CGIOperandList(Record *R) : TheDef(R) {
136 PrintFatalError("'" + TheDef->getName() + "' does not have an operand named '$" +
156 PrintFatalError(TheDef->getName() + ": Illegal operand name: '" + Op + "'");
166 PrintFatalError(TheDef->getName() + ": illegal empty suboperand name in '" +Op +"'");
176 PrintFatalError(TheDef->getName() + ": Illegal to refer to"
186 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
194 PrintFatalError(TheDef->getName() + ": unknown suboperand name in '" + Op + "'");
292 : TheDef(R), Operands(R), InferredFrom(0) {
517 CodeGenInstAlias::CodeGenInstAlias(Record *R, CodeGenTarget &T) : TheDef(R) {
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| CodeGenSchedule.cpp | 80 if ((*RI)->match((*I)->TheDef->getName()))
81 Elts.insert((*I)->TheDef);
219 Record *SchedDef = (*I)->TheDef;
298 findRWs(WI->TheDef->getValueAsListOfDefs("Writes"), WI->Sequence,
351 if (I->TheDef == Def)
359 Record *ReadDef = SchedReads[i].TheDef;
414 SchedRW.TheDef ? SchedRW.TheDef->getValueAsInt("Repeat") : 1;
440 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
443 AliasDef = AliasRW.TheDef;
[all...] |
| AsmWriterEmitter.cpp | 104 << FirstInst.CGI->TheDef->getName() << ":\n";
107 << SimilarInsts[i].CGI->TheDef->getName() << ":\n";
118 FirstInst.CGI->TheDef->getName(),
124 AWI.CGI->TheDef->getName(),
167 InstrsForCase[idx] += Inst->CGI->TheDef->getName();
174 InstrsForCase.push_back(Inst->CGI->TheDef->getName());
295 (*I)->TheDef->getName() != "PHI")
421 << NumberedInstructions[i]->TheDef->getName() << "\n";
435 << NumberedInstructions[i]->TheDef->getName() << "\n";
551 AsmName = Reg.TheDef->getValueAsString("AsmName")
[all...] |
| CodeGenInstruction.h | 128 Record *TheDef; // The actual record containing this OperandList.
202 Record *TheDef; // The actual record defining this instruction.
279 Record *TheDef; // The actual record defining this InstAlias.
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| SubtargetEmitter.cpp | 682 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes"))
683 return SchedWrite.TheDef;
690 if (AliasRW.TheDef->getValueInit("SchedModel")->isComplete()) {
691 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
696 PrintFatalError(AliasRW.TheDef->getLoc(), "Multiple aliases "
699 AliasDef = AliasRW.TheDef;
711 || SchedWrite.TheDef == (*WRI)->getValueAsDef("WriteType")) {
725 + SchedWrite.TheDef->getName());
735 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance"))
736 return SchedRead.TheDef;
[all...] |
| CodeGenRegisters.h | 37 Record *const TheDef;
96 Record *TheDef;
109 // Extract more information from TheDef. This is used to build an object
238 Record *TheDef;
273 Record *getDef() const { return TheDef; }
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| CodeGenRegisters.cpp | 31 : TheDef(R), EnumValue(Enum), LaneMask(0) {
39 : TheDef(0), Name(N), Namespace(Nspace), EnumValue(Enum), LaneMask(0) {
51 if (!TheDef)
54 std::vector<Record*> Comps = TheDef->getValueAsListOfDefs("ComposedOf");
57 PrintFatalError(TheDef->getLoc(),
63 PrintFatalError(TheDef->getLoc(), "Ambiguous ComposedOf entries");
67 TheDef->getValueAsListOfDefs("CoveringSubRegIndices");
70 PrintFatalError(TheDef->getLoc(),
101 : TheDef(R),
112 std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices")
[all...] |
| RegisterInfoEmitter.cpp | 78 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
320 Record *Reg = Regs[i]->TheDef;
338 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
387 Record *Reg = Regs[i]->TheDef;
443 Record *Reg = Regs[i]->TheDef;
451 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
832 OS << " { " << getQualifiedName(Roots.front()->TheDef);
834 OS << ", " << getQualifiedName(Roots[r]->TheDef);
[all...] |
| FixedLenDecoderEmitter.cpp | 375 BitsInit &Bits = getBitsField(*AllInstructions[Opcode]->TheDef, "Inst");
383 AllInstructions[Opcode]->TheDef->getValueAsBitsInit("SoftFail");
395 return AllInstructions[Opcode]->TheDef->getName();
831 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n";
[all...] |
| CodeGenDAGPatterns.h | 733 if (Intrinsics[i].TheDef == R) return Intrinsics[i];
735 if (TgtIntrinsics[i].TheDef == R) return TgtIntrinsics[i];
749 if (Intrinsics[i].TheDef == R) return i;
751 if (TgtIntrinsics[i].TheDef == R) return i + Intrinsics.size();
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| PseudoLoweringEmitter.cpp | 211 << Source.TheDef->getName() << ": {\n"
215 << Dest.TheDef->getName() << ");\n";
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| CodeGenTarget.cpp | 292 return Rec1->TheDef->getName() < Rec2->TheDef->getName();
419 TheDef = R;
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| CodeEmitterGen.cpp | 262 Record *R = CGI->TheDef;
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| CodeGenMapTable.cpp | 376 Record *CurInstr = NumberedInstructions[i]->TheDef;
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| DAGISelMatcherEmitter.cpp | 443 OS << "TARGET_VAL(" << getQualifiedName(Reg->TheDef) << "),\n";
448 OS << getQualifiedName(Reg->TheDef) << ",\n";
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| X86RecognizableInstr.cpp | 213 Rec = insn.TheDef;
284 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
[all...] |
| IntrinsicEmitter.cpp | 697 PrintFatalError("Intrinsic '" + Ints[i].TheDef->getName() +
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| CodeGenDAGPatterns.cpp | [all...] |
| DAGISelMatcherGen.cpp | [all...] |
