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    Searched refs:VEX (Results 1 - 4 of 4) sorted by null

  /external/valgrind/main/
Android.mk 36 external/valgrind/main/VEX/pub \
73 VEX/priv/main_globals.c \
74 VEX/priv/main_main.c \
75 VEX/priv/main_util.c \
76 VEX/priv/ir_defs.c \
77 VEX/priv/ir_match.c \
78 VEX/priv/ir_opt.c \
79 VEX/priv/guest_generic_bb_to_IR.c \
80 VEX/priv/guest_generic_x87.c \
81 VEX/priv/guest_mips_helpers.c
    [all...]
  /external/llvm/lib/Target/X86/MCTargetDesc/
X86BaseInfo.h 432 /// VEX - The opcode prefix used by AVX instructions
434 VEX = 1U << 0,
446 /// operand 3 with VEX.vvvv.
454 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
460 // VEX_LIG - Specifies that this instruction ignores the L-bit in the VEX
X86MCCodeEmitter.cpp 61 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
65 // VEX.VVVV => XMM9 => ~9
442 /// called VEX.
477 // XOP: Use XOP prefix byte 0x8f instead of VEX.
480 // VEX_5M (VEX m-mmmmm field):
491 // VEX_4V (VEX vvvv field): a register specifier
557 case X86II::A6: // Bypass: Not used by VEX
558 case X86II::A7: // Bypass: Not used by VEX
559 case X86II::TB: // Bypass: Not used by VEX
705 // VEX opcode prefix can have 2 or 3 byte
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  /external/llvm/lib/Target/X86/
X86CodeEmitter.cpp 760 // In the VEX prefix, registers are seen sequencially from 0-15 and encoded
764 // VEX.VVVV => XMM9 => ~9
847 // XOP: Use XOP prefix byte 0x8f instead of VEX.
850 // VEX_5M (VEX m-mmmmm field):
861 // VEX_4V (VEX vvvv field): a register specifier
    [all...]

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