| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrBuilder.h | 36 return MIB.addImm(Offset).addFrameIndex(FI);
38 return MIB.addFrameIndex(FI).addImm(Offset);
|
| PPCBranchSelector.cpp | 162 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
164 BuildMI(MBB, I, dl, TII->get(PPC::BDZ)).addImm(2);
166 BuildMI(MBB, I, dl, TII->get(PPC::BDZ8)).addImm(2);
168 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ)).addImm(2);
170 BuildMI(MBB, I, dl, TII->get(PPC::BDNZ8)).addImm(2);
|
| PPCFrameLowering.cpp | 153 .addImm(UsedRegMask);
157 .addImm(UsedRegMask);
162 .addImm(UsedRegMask >> 16);
166 .addImm(UsedRegMask >> 16);
171 .addImm(UsedRegMask >> 16);
175 .addImm(UsedRegMask >> 16);
179 .addImm(UsedRegMask & 0xFFFF);
366 .addImm(FPOffset/4)
372 .addImm(LROffset / 4)
383 .addImm(FPOffset
[all...] |
| PPCRegisterInfo.cpp | 215 .addImm(FrameSize);
218 .addImm(0)
222 .addImm(0)
236 .addImm(maxCallFrameSize);
241 .addImm(maxCallFrameSize)
252 .addImm(maxCallFrameSize);
257 .addImm(maxCallFrameSize)
303 .addImm(getPPCRegisterNumbering(SrcReg) * 4)
304 .addImm(0)
305 .addImm(31)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrBuilder.h | 93 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
99 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
117 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
118 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
133 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
137 MIB.addImm(AM.Disp);
177 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonExpandPredSpillCode.cpp | 92 HEXAGON_RESERVED_REG_1).addImm(Offset);
101 .addImm(0).addReg(HEXAGON_RESERVED_REG_2);
104 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
110 .addImm(0)
118 addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2);
136 HEXAGON_RESERVED_REG_1).addImm(Offset);
144 .addImm(0);
149 HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset);
153 .addImm(0);
159 HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset)
[all...] |
| HexagonRegisterInfo.cpp | 177 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
184 dstReg).addReg(FrameReg).addImm(Offset);
206 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
213 resReg).addReg(FrameReg).addImm(Offset);
226 TII.get(Hexagon::CONST32_Int_Real), resReg).addImm(Offset);
236 resReg).addReg(FrameReg).addImm(Offset);
244 TII.get(Hexagon::CONST32_Int_Real), dstReg).addImm(Offset);
|
| HexagonSplitTFRCondSets.cpp | 134 addImm(MI->getOperand(3).getImm());
155 addImm(MI->getOperand(2).getImm());
184 DestReg).addReg(SrcReg1).addImm(Immed1);
187 DestReg).addReg(SrcReg1).addImm(Immed2);
|
| HexagonFrameLowering.cpp | 149 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(0);
153 HEXAGON_RESERVED_REG_1).addImm(NumBytes);
159 BuildMI(MBB, InsertPt, dl, TII.get(Hexagon::ALLOCFRAME)).addImm(NumBytes);
198 .addImm(NumBytes);
200 BuildMI(MBB, MBBI, dl, TII.get(Hexagon::DEALLOCFRAME)).addImm(NumBytes);
|
| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 38 MCInstBuilder &addImm(int64_t Val) {
|
| /external/llvm/lib/Target/Sparc/ |
| SparcFrameLowering.cpp | 56 .addReg(SP::O6).addImm(NumBytes);
61 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
64 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
81 BuildMI(MBB, I, dl, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
|
| SparcInstrInfo.cpp | 122 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
206 .addMBB(UnCondBrIter->getOperand(0).getMBB()).addImm(BranchCode);
248 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
250 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
307 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
310 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
313 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | [all...] |
| Thumb2RegisterInfo.cpp | 50 .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0)
|
| Thumb1InstrInfo.cpp | 75 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
102 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
|
| ARMExpandPseudoInsts.cpp | 558 MIB.addImm(Lane);
635 LO16 = LO16.addImm(SOImmValV1);
636 HI16 = HI16.addImm(SOImmValV2)
[all...] |
| Thumb2InstrInfo.cpp | 144 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
170 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
194 .addImm(NumBytes)
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
201 .addImm(NumBytes >> 16)
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
242 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags));
282 .addImm(ThisVal)).setMIFlags(MIFlags)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreRegisterInfo.cpp | 194 .addImm(Offset);
200 .addImm(Offset);
205 .addImm(Offset);
222 .addImm(Offset);
228 .addImm(Offset);
233 .addImm(Offset);
252 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
|
| XCoreInstrInfo.cpp | 344 .addImm(0);
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
373 .addImm(0);
386 .addImm(0);
394 .addFrameIndex(FrameIx).addImm(0).addImm(Offset).addMetadata(MDPtr);
|
| /external/llvm/lib/Target/MBlaze/ |
| MBlazeFrameLowering.cpp | 256 .addFrameIndex(FI).addImm(0);
264 .addFrameIndex(R17FI).addImm(0);
267 .addFrameIndex(R18FI).addImm(0);
275 .addFrameIndex(MSRFI).addImm(0);
278 .addFrameIndex(MSRFI).addImm(0);
285 .addFrameIndex(R18FI).addImm(0);
288 .addFrameIndex(R17FI).addImm(0);
294 .addFrameIndex(VFI[--i]).addImm(0);
367 .addReg(MBlaze::R1).addImm(-StackSize);
372 .addReg(MBlaze::R15).addReg(MBlaze::R1).addImm(RAOffset)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.cpp | 113 .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0)
180 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)).addImm(FrameSize);
185 BuildMI(MBB, I, DL, get(Mips::SaveRaF16)). addImm(Base);
202 MIB1.addImm(-4);
206 MIB2.addImm(-8);
210 MIB3.addImm(-12);
222 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)).addImm(FrameSize);
231 BuildMI(MBB, I, DL, get(Mips::RestoreRaF16)). addImm(Base);
242 MIB1.addImm(-4)
[all...] |
| MipsLongBranch.cpp | 284 .addReg(Mips::SP).addImm(-8);
286 .addReg(Mips::SP).addImm(0);
290 .append(BuildMI(*MF, DL, TII->get(Mips::LUi), Mips::AT).addImm(Hi));
295 .addReg(Mips::AT).addImm(Lo);
299 .addReg(Mips::SP).addImm(0);
304 .addReg(Mips::SP).addImm(8));
331 .addReg(Mips::SP_64).addImm(-16);
333 .addReg(Mips::SP_64).addImm(0);
335 .addImm(Highest);
337 .addReg(Mips::AT_64).addImm(Higher)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | 51 .addImm(0);
57 .addImm(0);
63 .addImm(A64SysReg::NZCV)
69 .addImm(A64SysReg::NZCV);
101 .addImm(0x1ff & -16);
106 .addImm(16);
116 .addImm(0);
124 .addFrameIndex(FrameIx).addImm(0)
125 .addImm(Offset)
420 .addImm(0
[all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430FrameLowering.cpp | 99 .addReg(MSP430::SPW).addImm(NumBytes);
162 .addReg(MSP430::SPW).addImm(CSSize);
171 .addReg(MSP430::SPW).addImm(NumBytes);
249 .addReg(MSP430::SPW).addImm(Amount);
258 .addReg(MSP430::SPW).addImm(Amount);
276 MSP430::SPW).addReg(MSP430::SPW).addImm(CalleeAmt);
|
| /external/llvm/lib/Target/R600/ |
| R600InstrInfo.cpp | 81 MIB.addImm(Imm);
659 MIB.addImm(0) // $update_exec_mask
660 .addImm(0); // $update_predicate
662 MIB.addImm(1) // $write
663 .addImm(0) // $omod
664 .addImm(0) // $dst_rel
665 .addImm(0) // $dst_clamp
667 .addImm(0) // $src0_neg
668 .addImm(0) // $src0_rel
669 .addImm(0) // $src0_ab
[all...] |
