| /external/llvm/include/llvm/MC/ |
| MCInstBuilder.h | 33 Inst.addOperand(MCOperand::CreateReg(Reg));
39 Inst.addOperand(MCOperand::CreateImm(Val));
45 Inst.addOperand(MCOperand::CreateFPImm(Val));
51 Inst.addOperand(MCOperand::CreateExpr(Val));
57 Inst.addOperand(MCOperand::CreateInst(Val));
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 348 Inst.addOperand(MCOperand::CreateReg(Reg));
359 Inst.addOperand(MCOperand::CreateReg(Reg));
378 Inst.addOperand(MCOperand::CreateReg(Reg));
390 Inst.addOperand(MCOperand::CreateReg(Reg));
398 Inst.addOperand(MCOperand::CreateReg(RegNo));
414 Inst.addOperand(MCOperand::CreateReg(Reg));
417 Inst.addOperand(MCOperand::CreateReg(Reg));
418 Inst.addOperand(MCOperand::CreateReg(Base));
419 Inst.addOperand(MCOperand::CreateImm(Offset));
435 Inst.addOperand(MCOperand::CreateReg(Reg))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 39 NopInst.addOperand(MCOperand::CreateImm(0));
40 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
41 NopInst.addOperand(MCOperand::CreateReg(0));
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
46 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
47 NopInst.addOperand(MCOperand::CreateReg(0));
48 NopInst.addOperand(MCOperand::CreateReg(0));
|
| Thumb1InstrInfo.cpp | 31 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
32 NopInst.addOperand(MCOperand::CreateReg(ARM::R8));
33 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
34 NopInst.addOperand(MCOperand::CreateReg(0));
|
| ARMExpandPseudoInsts.cpp | 81 UseMI.addOperand(MO);
83 DefMI.addOperand(MO);
400 MIB.addOperand(MI.getOperand(OpIdx++));
403 MIB.addOperand(MI.getOperand(OpIdx++));
404 MIB.addOperand(MI.getOperand(OpIdx++));
407 MIB.addOperand(MI.getOperand(OpIdx++));
417 MIB.addOperand(MI.getOperand(OpIdx++));
418 MIB.addOperand(MI.getOperand(OpIdx++));
425 MIB.addOperand(MO);
452 MIB.addOperand(MI.getOperand(OpIdx++))
[all...] |
| ARMAsmPrinter.cpp | [all...] |
| ARMMCInstLower.cpp | 123 OutMI.addOperand(MCOp);
|
| Thumb2SizeReduction.cpp | 469 MIB.addOperand(MI->getOperand(0));
470 MIB.addOperand(MI->getOperand(1));
483 MIB.addOperand(MI->getOperand(OpNum));
530 .addOperand(MI->getOperand(0))
531 .addOperand(MI->getOperand(1))
692 MIB.addOperand(MI->getOperand(0));
707 MIB.addOperand(MI->getOperand(i));
789 MIB.addOperand(MI->getOperand(0));
818 MIB.addOperand(MO);
[all...] |
| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 541 instr.addOperand(MCOperand::CreateReg(RD));
542 instr.addOperand(MCOperand::CreateReg(RB));
543 instr.addOperand(MCOperand::CreateReg(RA));
549 instr.addOperand(MCOperand::CreateReg(RD));
550 instr.addOperand(MCOperand::CreateReg(RA));
551 instr.addOperand(MCOperand::CreateReg(RB));
557 instr.addOperand(MCOperand::CreateReg(RD));
558 instr.addOperand(MCOperand::CreateReg(RA));
568 instr.addOperand(MCOperand::CreateReg(RD));
569 instr.addOperand(MCOperand::CreateImm(insn&0x3FFF))
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 68 MI->addOperand(*MF, MachineOperand::CreateReg(RegNo,
84 MI->addOperand(*MF, MachineOperand::CreateImm(Val));
89 MI->addOperand(*MF, MachineOperand::CreateCImm(Val));
94 MI->addOperand(*MF, MachineOperand::CreateFPImm(Val));
100 MI->addOperand(*MF, MachineOperand::CreateMBB(MBB, TargetFlags));
105 MI->addOperand(*MF, MachineOperand::CreateFI(Idx));
112 MI->addOperand(*MF, MachineOperand::CreateCPI(Idx, Offset, TargetFlags));
118 MI->addOperand(*MF, MachineOperand::CreateTargetIndex(Idx, Offset,
125 MI->addOperand(*MF, MachineOperand::CreateJTI(Idx, TargetFlags));
132 MI->addOperand(*MF, MachineOperand::CreateGA(GV, Offset, TargetFlags))
[all...] |
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 245 Inst.addOperand(MCOperand::CreateReg(getReg()));
251 Inst.addOperand(MCOperand::CreateImm(0));
253 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
255 Inst.addOperand(MCOperand::CreateExpr(Expr));
267 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
347 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
354 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
362 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
370 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum));
374 Inst.addOperand(MCOperand::CreateReg(Reg.RegNum))
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 246 Inst.addOperand(MCOperand::CreateReg(Register));
257 Inst.addOperand(MCOperand::CreateReg(Register));
268 Inst.addOperand(MCOperand::CreateReg(Register));
279 Inst.addOperand(MCOperand::CreateReg(Register));
290 Inst.addOperand(MCOperand::CreateReg(Register));
301 Inst.addOperand(MCOperand::CreateReg(Register));
313 Inst.addOperand(MCOperand::CreateReg(Register));
324 Inst.addOperand(MCOperand::CreateReg(Register));
336 Inst.addOperand(MCOperand::CreateReg(Register));
347 Inst.addOperand(MCOperand::CreateReg(Register))
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 580 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateUpper16(Expr, *Ctx)));
582 MI.addOperand(MCOperand::CreateExpr(ARMMCExpr::CreateLower16(Expr, *Ctx)));
584 MI.addOperand(MCOperand::CreateExpr(Expr));
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 257 OutMI.addOperand(OutMI.getOperand(0));
258 OutMI.addOperand(OutMI.getOperand(0));
280 Inst.addOperand(Saved);
331 Inst.addOperand(Saved);
373 OutMI.addOperand(MCOp);
471 OutMI.addOperand(Saved);
497 OutMI.addOperand(Saved);
607 OutMI.addOperand(MCOperand::CreateReg(X86::R10));
608 OutMI.addOperand(MCOperand::CreateReg(X86::RAX));
651 LEA.addOperand(MCOperand::CreateReg(X86::RDI)); // des
[all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 166 .addOperand(MI->getOperand(0))
167 .addOperand(MI->getOperand(1))
177 .addOperand(MI->getOperand(3))
178 .addOperand(MI->getOperand(4))
179 .addOperand(MI->getOperand(5))
180 .addOperand(MI->getOperand(6));
182 .addOperand(MI->getOperand(2))
183 .addOperand(MI->getOperand(4))
184 .addOperand(MI->getOperand(5))
185 .addOperand(MI->getOperand(6))
[all...] |
| AMDGPUMCInstLower.cpp | 60 OutMI.addOperand(MCOp);
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.cpp | 167 mcInst.addOperand(MCOperand::CreateReg(llvmRegnum));
278 MI.addOperand(MCOperand::CreateExpr(Expr));
378 mcInst.addOperand(MCOperand::CreateReg(X86::XMM0 + (immediate >> 4)));
381 mcInst.addOperand(MCOperand::CreateReg(X86::YMM0 + (immediate >> 4)));
413 mcInst.addOperand(MCOperand::CreateImm(immediate));
444 mcInst.addOperand(MCOperand::CreateReg(X86::x)); break;
624 mcInst.addOperand(baseReg);
625 mcInst.addOperand(scaleAmount);
626 mcInst.addOperand(indexReg);
630 mcInst.addOperand(displacement)
[all...] |
| /frameworks/compile/slang/ |
| slang_rs_backend.cpp | 261 mExportVarMetadata->addOperand(
271 mRSObjectSlotsMetadata->addOperand(llvm::MDNode::get(mLLVMContext,
402 mExportFuncMetadata->addOperand(
432 mExportForEachNameMetadata->addOperand(
440 mExportForEachSignatureMetadata->addOperand(
471 mExportTypeMetadata->addOperand(
498 StructInfoMetadata->addOperand(
|
| slang_rs_metadata_spec_encoder.cpp | 285 RecordInfoMetadata->addOperand(llvm::MDNode::get(mModule->getContext(),
330 mVarInfoMetadata->addOperand(llvm::MDNode::get(mModule->getContext(),
356 mFuncInfoMetadata->addOperand(llvm::MDNode::get(mModule->getContext(),
434 RSMetadataStrTab->addOperand(llvm::MDNode::get(mModule->getContext(),
476 RSTypeInfo->addOperand(llvm::MDNode::get(mModule->getContext(),
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 780 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
782 Inst.addOperand(MCOperand::CreateExpr(Expr));
790 Inst.addOperand(MCOperand::CreateImm(EncodedVal));
796 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
805 Inst.addOperand(MCOperand::CreateImm(LSB + CE->getValue() - 1));
810 Inst.addOperand(MCOperand::CreateImm(getCondCode()));
817 Inst.addOperand(MCOperand::CreateImm(64 - CE->getValue()));
827 Inst.addOperand(MCOperand::CreateImm(ImmVal));
832 Inst.addOperand(MCOperand::CreateImm(0));
838 Inst.addOperand(MCOperand::CreateImm(Encoded))
[all...] |
| /external/llvm/unittests/IR/ |
| MetadataTest.cpp | 143 NMD->addOperand(n);
144 NMD->addOperand(n2);
|
| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| MBlazeAsmParser.cpp | 186 Inst.addOperand(MCOperand::CreateImm(0));
188 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
190 Inst.addOperand(MCOperand::CreateExpr(Expr));
195 Inst.addOperand(MCOperand::CreateReg(getReg()));
211 Inst.addOperand(MCOperand::CreateReg(getMemBase()));
215 Inst.addOperand(MCOperand::CreateReg(RegOff));
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMCInstLower.cpp | 93 MCI.addOperand(MCO);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430BranchSelector.cpp | 156 .addImm(4).addOperand(Cond[0]);
|
