| /dalvik/vm/compiler/codegen/arm/ |
| ArmRallocUtil.cpp | 52 extern void dvmCompilerClobberCallRegs(CompilationUnit *cUnit)
54 dvmCompilerClobber(cUnit, r0);
55 dvmCompilerClobber(cUnit, r1);
56 dvmCompilerClobber(cUnit, r2);
57 dvmCompilerClobber(cUnit, r3);
58 dvmCompilerClobber(cUnit, r9); // Need to do this?, be conservative
59 dvmCompilerClobber(cUnit, r11);
60 dvmCompilerClobber(cUnit, r12);
61 dvmCompilerClobber(cUnit, r14lr);
65 extern void dvmCompilerClobberHandlerRegs(CompilationUnit *cUnit)
[all...] |
| CodegenDriver.cpp | 30 static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
32 int regCardBase = dvmCompilerAllocTemp(cUnit);
33 int regCardNo = dvmCompilerAllocTemp(cUnit);
34 ArmLIR *branchOver = genCmpImmBranch(cUnit, kArmCondEq, valReg, 0);
35 loadWordDisp(cUnit, r6SELF, offsetof(Thread, cardTable),
37 opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
38 storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
40 ArmLIR *target = newLIR0(cUnit, kArmPseudoTargetLabel);
43 dvmCompilerFreeTemp(cUnit, regCardBase);
44 dvmCompilerFreeTemp(cUnit, regCardNo)
[all...] |
| ArchFactory.cpp | 29 static TGT_LIR *genRegImmCheck(CompilationUnit *cUnit,
34 TGT_LIR *branch = genCmpImmBranch(cUnit, cond, reg, checkValue);
35 if (cUnit->jitMode == kJitMethod) {
36 BasicBlock *bb = cUnit->curBlock;
38 ArmLIR *exceptionLabel = (ArmLIR *) cUnit->blockLabelList;
48 return genCheckCommon(cUnit, dOffset, branch, pcrLabel);
57 static TGT_LIR *genNullCheck(CompilationUnit *cUnit, int sReg, int mReg,
61 if (dvmIsBitSet(cUnit->regPool->nullCheckedRegs, sReg)) {
64 dvmSetBit(cUnit->regPool->nullCheckedRegs, sReg);
65 return genRegImmCheck(cUnit, kArmCondEq, mReg, 0, dOffset, pcrLabel)
[all...] |
| GlobalOptimizations.cpp | 25 static void applyRedundantBranchElimination(CompilationUnit *cUnit)
29 for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn;
30 thisLIR != (ArmLIR *) cUnit->lastLIRInsn;
55 (nextLIR = (ArmLIR *) cUnit->lastLIRInsn))
62 void dvmCompilerApplyGlobalOptimizations(CompilationUnit *cUnit)
64 applyRedundantBranchElimination(cUnit);
|
| /dalvik/vm/compiler/codegen/arm/armv5te/ |
| MethodCodegenDriver.cpp | 17 void dvmCompilerMethodMIR2LIR(CompilationUnit *cUnit)
|
| /dalvik/vm/compiler/codegen/mips/mips/ |
| MethodCodegenDriver.cpp | 17 void dvmCompilerMethodMIR2LIR(CompilationUnit *cUnit)
|
| /dalvik/vm/compiler/codegen/arm/FP/ |
| ThumbPortableFP.cpp | 18 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
22 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
26 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir);
28 static bool handleExecuteInlineC(CompilationUnit *cUnit, MIR *mir);
30 static bool genConversion(CompilationUnit *cUnit, MIR *mir)
32 return genConversionPortable(cUnit, mir);
35 static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir,
39 return genArithOpFloatPortable(cUnit, mir, rlDest, rlSrc1, rlSrc2);
42 static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir,
46 return genArithOpDoublePortable(cUnit, mir, rlDest, rlSrc1, rlSrc2)
[all...] |
| ThumbVFP.cpp | 27 static void loadValueAddressDirect(CompilationUnit *cUnit, RegLocation rlSrc,
30 rlSrc = rlSrc.wide ? dvmCompilerUpdateLocWide(cUnit, rlSrc) :
31 dvmCompilerUpdateLoc(cUnit, rlSrc);
34 dvmCompilerFlushRegWide(cUnit, rlSrc.lowReg, rlSrc.highReg);
36 dvmCompilerFlushReg(cUnit, rlSrc.lowReg);
39 dvmCompilerClobber(cUnit, rDest);
40 dvmCompilerLockTemp(cUnit, rDest);
41 opRegRegImm(cUnit, kOpAdd, rDest, r5FP,
42 dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2);
45 static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir
[all...] |
| /dalvik/vm/compiler/codegen/ |
| Ralloc.h | 40 static inline int dvmCompilerS2VReg(CompilationUnit *cUnit, int sReg)
43 return DECODE_REG(dvmConvertSSARegToDalvik(cUnit, sReg));
47 static inline void dvmCompilerResetNullCheck(CompilationUnit *cUnit)
49 dvmClearAllBits(cUnit->regPool->nullCheckedRegs);
55 * dataflow analysis and refer to slot numbers in the cUnit->regLocation
57 * entries in the cUnit->reglocation[] array. Therefore, when location
67 static inline bool dvmCompilerLiveOut(CompilationUnit *cUnit, int sReg)
79 extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
82 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
84 extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit,
[all...] |
| CompilerCodegen.h | 30 void dvmCompilerMIR2LIR(CompilationUnit *cUnit);
32 void dvmCompilerMIR2LIR(CompilationUnit *cUnit, JitTranslationInfo* info);
36 void dvmCompilerMethodMIR2LIR(CompilationUnit *cUnit);
39 void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info);
45 void dvmJitInstallClassObjectPointers(CompilationUnit *cUnit,
52 void dvmCompilerCodegenDump(CompilationUnit *cUnit);
58 void dvmCompilerLocalRegAlloc(CompilationUnit *cUnit);
61 void dvmCompilerInitializeRegAlloc(CompilationUnit *cUnit);
76 void dvmCompilerGenMemBarrier(CompilationUnit *cUnit, int barrierKind);
|
| CodegenFactory.cpp | 35 static TGT_LIR *loadWordDisp(CompilationUnit *cUnit, int rBase,
38 return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
42 static TGT_LIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
45 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
53 static void loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc,
56 rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
58 genRegCopy(cUnit, reg1, rlSrc.lowReg);
60 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
63 loadWordDisp(cUnit, rFP, dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2
[all...] |
| RallocUtil.cpp | 34 * dataflow analysis and refer to slot numbers in the cUnit->regLocation
36 * entries in the cUnit->reglocation[] array. Therefore, when location
46 extern void dvmCompilerResetRegPool(CompilationUnit *cUnit)
49 for (i=0; i < cUnit->regPool->numCoreTemps; i++) {
50 cUnit->regPool->coreTemps[i].inUse = false;
52 for (i=0; i < cUnit->regPool->numFPTemps; i++) {
53 cUnit->regPool->FPTemps[i].inUse = false;
83 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
85 int numTemps = cUnit->regPool->numCoreTemps;
86 RegisterInfo *p = cUnit->regPool->coreTemps
[all...] |
| /dalvik/vm/compiler/codegen/arm/Thumb/ |
| Ralloc.cpp | 29 int dvmCompilerAllocTypedTempPair(CompilationUnit *cUnit, bool fpHint,
35 lowReg = dvmCompilerAllocTemp(cUnit);
36 highReg = dvmCompilerAllocTemp(cUnit);
41 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
43 return dvmCompilerAllocTemp(cUnit);
|
| Gen.cpp | 50 static int genTraceProfileEntry(CompilationUnit *cUnit)
54 newLIR1(cUnit, kArm16BitData, addr & 0xffff);
55 newLIR1(cUnit, kArm16BitData, (addr >> 16) & 0xffff);
56 cUnit->chainCellOffsetLIR =
57 (LIR *) newLIR1(cUnit, kArm16BitData, CHAIN_CELL_OFFSET_TAG);
58 cUnit->headerSize = 6;
62 newLIR2(cUnit, kThumbMovRR_H2L, r0, r15pc);
63 newLIR2(cUnit, kThumbSubRI8, r0, 10);
64 newLIR3(cUnit, kThumbLdrRRI5, r0, r0, 0);
65 newLIR3(cUnit, kThumbLdrRRI5, r1, r0, 0)
[all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Ralloc.h | 44 static inline int dvmCompilerS2VReg(CompilationUnit *cUnit, int sReg)
47 return DECODE_REG(dvmConvertSSARegToDalvik(cUnit, sReg));
51 static inline void dvmCompilerResetNullCheck(CompilationUnit *cUnit)
53 dvmClearAllBits(cUnit->regPool->nullCheckedRegs);
59 * dataflow analysis and refer to slot numbers in the cUnit->regLocation
61 * entries in the cUnit->reglocation[] array. Therefore, when location
71 static inline bool dvmCompilerLiveOut(CompilationUnit *cUnit, int sReg)
83 extern RegLocation dvmCompilerEvalLoc(CompilationUnit *cUnit, RegLocation loc,
86 extern void dvmCompilerClobber(CompilationUnit *cUnit, int reg);
88 extern RegLocation dvmCompilerUpdateLoc(CompilationUnit *cUnit,
[all...] |
| CodegenFactory.cpp | 29 static MipsLIR *loadWordDisp(CompilationUnit *cUnit, int rBase, int displacement,
32 return loadBaseDisp(cUnit, NULL, rBase, displacement, rDest, kWord,
36 static MipsLIR *storeWordDisp(CompilationUnit *cUnit, int rBase,
39 return storeBaseDisp(cUnit, rBase, displacement, rSrc, kWord);
47 static void loadValueDirect(CompilationUnit *cUnit, RegLocation rlSrc,
50 rlSrc = dvmCompilerUpdateLoc(cUnit, rlSrc);
52 genRegCopy(cUnit, reg1, rlSrc.lowReg);
54 loadWordDisp(cUnit, rSELF, offsetof(Thread, interpSave.retval), reg1);
57 loadWordDisp(cUnit, rFP, dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2
[all...] |
| Codegen.h | 32 static MipsLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
34 static MipsLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
38 static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir,
42 static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir,
46 static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir);
48 static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir);
50 static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir);
64 extern int dvmCompilerAllocTypedTempPair(CompilationUnit *cUnit,
67 extern int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint,
70 extern MipsLIR* dvmCompilerRegCopyNoInsert(CompilationUnit *cUnit, int rDest
[all...] |
| CodegenDriver.cpp | 30 static void markCard(CompilationUnit *cUnit, int valReg, int tgtAddrReg)
32 int regCardBase = dvmCompilerAllocTemp(cUnit);
33 int regCardNo = dvmCompilerAllocTemp(cUnit);
34 MipsLIR *branchOver = opCompareBranch(cUnit, kMipsBeq, valReg, r_ZERO);
35 loadWordDisp(cUnit, rSELF, offsetof(Thread, cardTable),
37 opRegRegImm(cUnit, kOpLsr, regCardNo, tgtAddrReg, GC_CARD_SHIFT);
38 storeBaseIndexed(cUnit, regCardBase, regCardNo, regCardBase, 0,
40 MipsLIR *target = newLIR0(cUnit, kMipsPseudoTargetLabel);
43 dvmCompilerFreeTemp(cUnit, regCardBase);
44 dvmCompilerFreeTemp(cUnit, regCardNo)
[all...] |
| RallocUtil.cpp | 36 * dataflow analysis and refer to slot numbers in the cUnit->regLocation
38 * entries in the cUnit->reglocation[] array. Therefore, when location
48 extern void dvmCompilerResetRegPool(CompilationUnit *cUnit)
51 for (i=0; i < cUnit->regPool->numCoreTemps; i++) {
52 cUnit->regPool->coreTemps[i].inUse = false;
54 for (i=0; i < cUnit->regPool->numFPTemps; i++) {
55 cUnit->regPool->FPTemps[i].inUse = false;
85 static RegisterInfo *getRegInfo(CompilationUnit *cUnit, int reg)
87 int numTemps = cUnit->regPool->numCoreTemps;
88 RegisterInfo *p = cUnit->regPool->coreTemps
[all...] |
| /dalvik/vm/compiler/codegen/arm/armv7-a-neon/ |
| MethodCodegenDriver.cpp | 40 static void genMethodInflateAndPunt(CompilationUnit *cUnit, MIR *mir,
58 dvmCompilerFlushAllRegs(cUnit);
61 opRegRegImm(cUnit, kOpAdd, oldStackSave, r5FP,
62 cUnit->method->registersSize * 4);
64 opRegRegImm(cUnit, kOpAdd, oldFP, oldStackSave, sizeof(StackSaveArea));
66 opRegRegImm(cUnit, kOpSub, newStackSave, r5FP, sizeof(StackSaveArea));
68 loadWordDisp(cUnit, r13sp, 0, savedPC);
69 loadConstant(cUnit, currentPC, (int) (cUnit->method->insns + mir->offset));
70 loadConstant(cUnit, method, (int) cUnit->method)
[all...] |
| /dalvik/vm/compiler/codegen/mips/Mips32/ |
| Gen.cpp | 49 static int genTraceProfileEntry(CompilationUnit *cUnit)
53 MipsLIR *executionCount = newLIR1(cUnit, kMips32BitData, addr);
54 cUnit->chainCellOffsetLIR =
55 (LIR *) newLIR1(cUnit, kMips32BitData, CHAIN_CELL_OFFSET_TAG);
56 cUnit->headerSize = 8;
59 MipsLIR *loadAddr = newLIR2(cUnit, kMipsLahi, r_A0, 0);
61 loadAddr = newLIR3(cUnit, kMipsLalo, r_A0, r_A0, 0);
63 newLIR3(cUnit, kMipsLw, r_A0, 0, r_A0);
64 newLIR3(cUnit, kMipsLw, r_A1, 0, r_A0);
65 newLIR3(cUnit, kMipsAddiu, r_A1, r_A1, 1)
[all...] |
| Ralloc.cpp | 29 int dvmCompilerAllocTypedTempPair(CompilationUnit *cUnit, bool fpHint,
38 lowReg = dvmCompilerAllocTempDouble(cUnit);
45 lowReg = dvmCompilerAllocTemp(cUnit);
46 highReg = dvmCompilerAllocTemp(cUnit);
51 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint, int regClass)
56 return dvmCompilerAllocTempFloat(cUnit);
59 return dvmCompilerAllocTemp(cUnit);
|
| /dalvik/vm/compiler/codegen/arm/Thumb2/ |
| Ralloc.cpp | 32 int dvmCompilerAllocTypedTempPair(CompilationUnit *cUnit,
44 lowReg = dvmCompilerAllocTempDouble(cUnit);
47 lowReg = dvmCompilerAllocTemp(cUnit);
48 highReg = dvmCompilerAllocTemp(cUnit);
54 int dvmCompilerAllocTypedTemp(CompilationUnit *cUnit, bool fpHint,
61 return dvmCompilerAllocTempFloat(cUnit);
62 return dvmCompilerAllocTemp(cUnit);
|
| Gen.cpp | 47 static int genTraceProfileEntry(CompilationUnit *cUnit)
51 newLIR1(cUnit, kArm16BitData, addr & 0xffff);
52 newLIR1(cUnit, kArm16BitData, (addr >> 16) & 0xffff);
53 cUnit->chainCellOffsetLIR =
54 (LIR *) newLIR1(cUnit, kArm16BitData, CHAIN_CELL_OFFSET_TAG);
55 cUnit->headerSize = 6;
59 newLIR2(cUnit, kThumb2LdrPcReln12, r0, 8);
60 newLIR3(cUnit, kThumbLdrRRI5, r1, r0, 0);
61 newLIR2(cUnit, kThumbAddRI8, r1, 1);
62 newLIR3(cUnit, kThumbStrRRI5, r1, r0, 0)
[all...] |
| /dalvik/vm/compiler/codegen/mips/FP/ |
| MipsFP.cpp | 22 extern void dvmCompilerFlushRegWideForV5TEVFP(CompilationUnit *cUnit,
24 extern void dvmCompilerFlushRegForV5TEVFP(CompilationUnit *cUnit, int reg);
27 static void loadValueAddress(CompilationUnit *cUnit, RegLocation rlSrc,
30 rlSrc = rlSrc.wide ? dvmCompilerUpdateLocWide(cUnit, rlSrc) :
31 dvmCompilerUpdateLoc(cUnit, rlSrc);
34 dvmCompilerFlushRegWideForV5TEVFP(cUnit, rlSrc.lowReg,
37 dvmCompilerFlushRegForV5TEVFP(cUnit, rlSrc.lowReg);
40 opRegRegImm(cUnit, kOpAdd, rDest, rFP,
41 dvmCompilerS2VReg(cUnit, rlSrc.sRegLow) << 2);
44 static bool genInlineSqrt(CompilationUnit *cUnit, MIR *mir
[all...] |
