| /system/core/libpixelflinger/arch-mips/ |
| t32cb16blend.S | 25 * blend one of 2 16bpp RGB pixels held in dreg selected by shift
28 * Assumes that the dreg data is little endian and that
36 .macro pixel dreg src fb shift
52 ext $t8,\dreg,\shift+6+5,5 # dst[\shift:15..11]
54 ext $t0,\dreg,\shift+5,6 # start green extraction dst[\shift:10..5]
62 ext $t0,\dreg,\shift,5 # start blue extraction dst[\shift:4..0]
87 .macro pixel dreg src fb shift
112 srl $t8,\dreg,\shift+6+5
134 srl $t8,\dreg,\shift+5
146 srl $t8,\dreg,\shif
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_arm_toIR.c | 646 /* Plain ("low level") read from a VFP Dreg. */
653 /* Architected read from a VFP Dreg. */
658 /* Plain ("low level") write to a VFP Dreg. */
666 /* Architected write to a VFP Dreg. Handles conditional writes to the
690 /* Plain ("low level") read from a Neon Integer Dreg. */
697 /* Architected read from a Neon Integer Dreg. */
702 /* Plain ("low level") write to a Neon Integer Dreg. */
710 /* Architected write to a Neon Integer Dreg. Handles conditional
2866 UInt dreg = get_neon_d_regno(theInstr); local
2890 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
2970 UInt dreg = ((theInstr >> 18) & 0x10) | ((theInstr >> 12) & 0xF); local
3024 UInt dreg = get_neon_d_regno(theInstr); local
4823 UInt dreg = get_neon_d_regno(theInstr); local
5240 UInt dreg = get_neon_d_regno(theInstr & ~(1 << 6)); local
5914 UInt dreg = get_neon_d_regno(theInstr); local
6633 UInt dreg = get_neon_d_regno(theInstr); local
7659 UInt dreg = get_neon_d_regno(theInstr); local
[all...] |
| host_arm_isel.c | 3646 HReg dreg = iselNeon64Expr(env, triop->arg1); local
[all...] |
| /external/v8/src/arm/ |
| simulator-arm.h | 161 void set_dw_register(int dreg, const int* dbl);
166 void set_d_register_from_double(int dreg, const double& dbl);
167 double get_double_from_d_register(int dreg);
|
| simulator-arm.cc | 910 void Simulator::set_dw_register(int dreg, const int* dbl) {
911 ASSERT((dreg >= 0) && (dreg < num_d_registers));
912 registers_[dreg] = dbl[0];
913 registers_[dreg + 1] = dbl[1];
[all...] |
| macro-assembler-arm.h | [all...] |
| macro-assembler-arm.cc | [all...] |
| /dalvik/vm/mterp/mips/ |
| header.S | 110 #define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/api/ |
| armCOMM_s.h | 611 ;// $dreg = "" don't stack any D registers
618 M_START $name, $rreg, $dreg
637 _M_GETDREGLIST $dreg
697 _M_GETDREGLIST $dreg
698 IF "$dreg"=""
702 IF "$dreg"="d8"
707 IF "$dreg"="d9"
712 IF "$dreg"="d10"
717 IF "$dreg"="d11"
722 IF "$dreg"="d12
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_s.h | 614 ;// $dreg = "" don't stack any D registers
621 M_START $name, $rreg, $dreg
640 _M_GETDREGLIST $dreg
700 _M_GETDREGLIST $dreg
701 IF "$dreg"=""
705 IF "$dreg"="d8"
710 IF "$dreg"="d9"
715 IF "$dreg"="d10"
720 IF "$dreg"="d11"
725 IF "$dreg"="d12
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.h | [all...] |
| macro-assembler-mips.cc | [all...] |
| /dalvik/vm/mterp/out/ |
| InterpAsm-mips.S | 117 #define GET_PREFETCHED_OPCODE(dreg, sreg) andi dreg, sreg, 255
[all...] |
