| /external/qemu/tcg/ppc/ |
| tcg-target.c | 442 tcg_out32 (s, OR | SAB (arg, ret, arg));
449 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
451 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
453 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
461 tcg_out32 (s, op1 | RT (ret) | RA (addr) | (offset & 0xffff));
464 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
474 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
477 tcg_out32 (s, MTSPR | RS (0) | CTR);
478 tcg_out32 (s, BCCTR | BO_ALWAYS | mask);
493 tcg_out32 (s, LWZ | RT (0) | RA (reg))
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 440 tcg_out32 (s, OR | SAB (arg, ret, arg));
447 tcg_out32 (s, op | RA (ra) | RS (rs) | sh | mb);
453 tcg_out32 (s, ADDI | RT (ret) | RA (0) | (arg & 0xffff));
455 tcg_out32 (s, ADDIS | RT (ret) | RA (0) | ((arg >> 16) & 0xffff));
457 tcg_out32 (s, ORI | RS (ret) | RA (ret) | (arg & 0xffff));
477 if (h16) tcg_out32 (s, ORIS | RS (ret) | RA (ret) | h16);
478 if (l16) tcg_out32 (s, ORI | RS (ret) | RA (ret) | l16);
494 tcg_out32 (s, B | (disp & 0x3fffffc) | mask);
497 tcg_out32 (s, MTSPR | RS (0) | CTR);
498 tcg_out32 (s, BCCTR | BO_ALWAYS | mask)
[all...] |
| /external/qemu/tcg/arm/ |
| tcg-target.c | 344 tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
349 tcg_out32(s, (cond << 28) | 0x0a000000 |
369 tcg_out32(s, (cond << 28) | 0x0b000000 |
375 tcg_out32(s, (cond << 28) | 0x012fff30 | rn);
380 tcg_out32(s, 0xfa000000 | ((offset & 2) << 23) |
387 tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
396 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
398 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
403 tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
405 tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21)
[all...] |
| /external/qemu/tcg/hppa/ |
| tcg-target.c | 346 tcg_out32(s, INSN_OR | INSN_T(ret) | INSN_R1(arg)
355 tcg_out32(s, INSN_LDO | INSN_R1(ret)
362 tcg_out32(s, INSN_LDIL | INSN_R2(ret) | reassemble_21(hi));
364 tcg_out32(s, INSN_LDO | INSN_R1(ret)
384 tcg_out32(s, op | reassemble_21(hi));
391 tcg_out32(s, op | INSN_R1(ret) | INSN_R2(addr) | INSN_IM14(offset));
412 tcg_out32(s, op | INSN_T(data) | INSN_R1(index) | INSN_R2(base));
429 tcg_out32(s, op | INSN_T(t) | INSN_R1(r1) | INSN_R2(r2));
436 tcg_out32(s, op | INSN_R1(t) | INSN_R2(r1) | INSN_IM11(val));
446 tcg_out32(s, INSN_MTCTL | INSN_R2(11) | INSN_R1(arg))
[all...] |
| /external/qemu/tcg/sparc/ |
| tcg-target.c | 289 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
296 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) |
303 tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
314 tcg_out32(s, SETHI | INSN_RD(ret) | ((arg & 0xfffffc00) >> 10));
361 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
371 tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) |
374 tcg_out32(s, LDUW | INSN_RD(ret) | INSN_RS1(ret) |
382 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(addr) |
386 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5) |
395 tcg_out32(s, op | INSN_RD(ret) | INSN_RS1(TCG_REG_I5)
[all...] |
| /external/qemu/tcg/x86_64/ |
| tcg-target.c | 281 tcg_out32(s, val);
285 tcg_out32(s, offset);
314 tcg_out32(s, offset);
352 tcg_out32(s, offset);
369 tcg_out32(s, arg);
372 tcg_out32(s, arg);
375 tcg_out32(s, arg);
376 tcg_out32(s, arg >> 32);
387 tcg_out32(s, disp);
431 tcg_out32(s, val)
[all...] |
| /external/qemu/tcg/i386/ |
| tcg-target.c | 430 tcg_out32(s, disp);
441 tcg_out32(s, offset);
451 tcg_out32(s, offset);
494 tcg_out32(s, offset);
531 tcg_out32(s, arg);
534 tcg_out32(s, arg);
537 tcg_out32(s, arg);
538 tcg_out32(s, arg >> 31 >> 1);
549 tcg_out32(s, val);
699 tcg_out32(s, val)
[all...] |
| /external/qemu/tcg/ |
| tcg.c | 105 static inline void tcg_out32(TCGContext *s, uint32_t v) function
[all...] |
