| /external/llvm/include/llvm/CodeGen/ |
| ValueTypes.h | 86 v16i32 = 35, // 16 x i32 enumerator in enum:llvm::MVT::SimpleValueType
227 SimpleTy == MVT::v8i64 || SimpleTy == MVT::v16i32);
284 case v16i32: return i32;
313 case v16i32:
401 case v16i32:
511 if (NumElements == 16) return MVT::v16i32;
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 215 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*4 },
216 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 16*2 + 4*3 },
219 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 4*1 + 16*2 + 2*1 },
244 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
245 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
394 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 4*16 + 1*6 + 1*8 + 1*4 },
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 153 case MVT::v16i32: return "v16i32";
216 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16);
|
| /external/llvm/lib/Target/R600/ |
| SIISelLowering.cpp | 56 addRegisterClass(MVT::v16i32, &AMDGPU::VReg_512RegClass);
63 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 94 case MVT::v16i32: return "MVT::v16i32";
|
