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/external/kernel-headers/original/asm-arm/
hardware.h	2 * linux/include/asm-arm/hardware.h
/external/llvm/test/Bitcode/
arm32_neon_vcnt_upgrade.ll	7 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1) 15 %tmp2 = call <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8> %tmp1) 20 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone 21 declare <8 x i8> @llvm.arm.neon.vcnt.v8i8(<8 x i8>) nounwind readnone
/external/llvm/test/CodeGen/ARM/
2009-04-08-FREM.ll	1 ; RUN: llc < %s -march=arm
2009-07-09-asm-p-constraint.ll	1 ; RUN: llc < %s -march=arm -mattr=+v6
2010-04-13-v2f64SplitArg.ll	1 ; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8
2012-09-18-ARMv4ISelBug.ll	1 ; RUN: llc < %s -march=arm -mcpu=arm7tdmi | FileCheck %s
arguments-nosplit-double.ll	1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
arguments-nosplit-i64.ll	1 ; RUN: llc < %s -mtriple=arm-linux-gnueabi | not grep r3
arm-asm.ll	1 ; RUN: llc < %s -march=arm
ctz.ll	1 ; RUN: llc < %s -march=arm -mattr=+v6t2 | FileCheck %s
fabss.ll	1 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 2 ; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s -check-prefix=NFP0 3 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 4 ; RUN: llc < %s -mtriple=arm-apple-ios -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
fadds.ll	1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 4 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
fdivs.ll	1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 4 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
fmuls.ll	1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s -check-prefix=VFP2 2 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s -check-prefix=NFP0 3 ; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s -check-prefix=CORTEXA8 4 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=CORTEXA9
fpow.ll	1 ; RUN: llc < %s -march=arm
ifcvt9.ll	1 ; RUN: llc < %s -march=arm
ispositive.ll	1 ; RUN: llc < %s -march=arm | FileCheck %s
ldstrexd.ll	10 %ldrexd = tail call %0 @llvm.arm.ldrexd(i8* %p) 27 %strexd = tail call i32 @llvm.arm.strexd(i32 %tmp4, i32 %tmp7, i8* %ptr) 31 declare %0 @llvm.arm.ldrexd(i8*) nounwind readonly 32 declare i32 @llvm.arm.strexd(i32, i32, i8*) nounwind
neon_arith1.ll	1 ; RUN: llc < %s -march=arm -mattr=+neon | grep vadd
section.ll	1 ; RUN: llc < %s -mtriple=arm-linux | FileCheck %s
tls2.ll	1 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \ 3 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi \
vargs_align.ll	1 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=EABI 2 ; RUN: llc < %s -march=arm -mtriple=arm-linux-gnu | FileCheck %s -check-prefix=OABI
vshll.ll	1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s 7 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 15 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) 23 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) 31 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >) 39 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >) 47 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >) 57 %tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >) 65 %tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >) 73 %tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >     [all...]
/external/llvm/test/ExecutionEngine/
2003-08-15-AllocaAssertion.ll	2 ; XFAIL: arm
/external/llvm/test/ExecutionEngine/MCJIT/
simpletest-remote.ll	2 ; XFAIL: arm, mips

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