| /external/llvm/test/CodeGen/X86/ |
| sse-align-5.ll | 3 define <2 x i64> @bar(<2 x i64>* %p) nounwind {
4 %t = load <2 x i64>* %p
5 ret <2 x i64> %t
|
| sse-align-7.ll | 5 define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
6 store <2 x i64> %x, <2 x i64>* %p
|
| sse-align-8.ll | 3 define void @bar(<2 x i64>* %p, <2 x i64> %x) nounwind {
4 store <2 x i64> %x, <2 x i64>* %p, align 8
|
| vec_set-A.ll | 3 define <2 x i64> @test1() nounwind {
5 ret <2 x i64> < i64 1, i64 0 >
|
| vsplit-and.ll | 3 define void @t0(<2 x i64>* %dst, <2 x i64> %src1, <2 x i64> %src2) nounwind readonly {
7 %cmp1 = icmp ne <2 x i64> %src1, zeroinitializer
8 %cmp2 = icmp ne <2 x i64> %src2, zeroinitializer
10 %t2 = sext <2 x i1> %t1 to <2 x i64>
11 store <2 x i64> %t2, <2 x i64>* %dst
15 define void @t2(<3 x i64>* %dst, <3 x i64> %src1, <3 x i64> %src2) nounwind readonly
[all...] |
| 2009-07-19-AsmExtraOperands.ll | 4 define i32 @atomic_cmpset_long(i64* %dst, i64 %exp, i64 %src) nounwind ssp noredzone noimplicitfloat {
6 %0 = call i8 asm sideeffect "\09lock ; \09\09\09cmpxchgq $2,$1 ;\09 sete\09$0 ;\09\091:\09\09\09\09# atomic_cmpset_long", "={ax},=*m,r,{ax},*m,~{memory},~{dirflag},~{fpsr},~{flags}"(i64* undef, i64 undef, i64 undef, i64* undef) nounwind ; <i8> [#uses=0]
|
| 2009-08-02-mmx-scalar-to-vector.ll | 5 define <1 x i64> @test(i64 %t) {
7 %t1 = insertelement <1 x i64> undef, i64 %t, i32 0
8 %t0 = bitcast <1 x i64> %t1 to x86_mmx
10 %t3 = bitcast x86_mmx %t2 to <1 x i64>
11 ret <1 x i64> %t3
|
| h-register-addressing-64.ll | 5 define double @foo8(double* nocapture inreg %p, i64 inreg %x) nounwind readonly {
6 %t0 = lshr i64 %x, 8
7 %t1 = and i64 %t0, 255
8 %t2 = getelementptr double* %p, i64 %t1
12 define float @foo4(float* nocapture inreg %p, i64 inreg %x) nounwind readonly {
13 %t0 = lshr i64 %x, 8
14 %t1 = and i64 %t0, 255
15 %t2 = getelementptr float* %p, i64 %t1
19 define i16 @foo2(i16* nocapture inreg %p, i64 inreg %x) nounwind readonly {
20 %t0 = lshr i64 %x,
[all...] |
| longlong-deadload.ll | 4 define void @test(i64* %P) nounwind {
9 %tmp1 = load i64* %P, align 8 ; <i64> [#uses=1]
10 %tmp2 = xor i64 %tmp1, 1 ; <i64> [#uses=1]
11 store i64 %tmp2, i64* %P, align 8
|
| pr14562.ll | 3 @temp1 = global i64 -77129852189294865, align 8
6 %x = load i64* @temp1, align 8
7 %s = shl i64 %x, 32
8 %t = trunc i64 %s to i32
9 %z = zext i32 %t to i64
10 store i64 %z, i64* @temp1, align 8
|
| select_const.ll | 3 define i64 @test1(i64 %x) nounwind {
5 %cmp = icmp eq i64 %x, 2
6 %add = add i64 %x, 1
7 %retval.0 = select i1 %cmp, i64 2, i64 %add
8 ret i64 %retval.0
|
| vec_set-8.ll | 7 define <2 x i64> @test(i64 %i) nounwind {
9 %tmp10 = insertelement <2 x i64> undef, i64 %i, i32 0
10 %tmp11 = insertelement <2 x i64> %tmp10, i64 0, i32 1
11 ret <2 x i64> %tmp11
|
| andimm8.ll | 6 define i64 @bra(i32 %zed) nounwind {
7 %t1 = zext i32 %zed to i64
8 %t2 = and i64 %t1, 4294967232
9 ret i64 %t2
14 define void @foo(i64 %zed, i64* %x) nounwind {
15 %t1 = and i64 %zed, -4
16 %t2 = or i64 %t1, 2
17 store i64 %t2, i64* %x, align
[all...] |
| /external/llvm/test/Feature/ |
| fold-fpcast.ll | 11 define i64 @test3() {
12 ret i64 bitcast (double 0x400921FB4D12D84A to i64)
16 ret double bitcast (i64 42 to double)
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2005-03-04-ShiftOverflow.ll | 4 define i1 @test(i64 %tmp.169) {
5 %tmp.1710 = lshr i64 %tmp.169, 1 ; <i64> [#uses=1]
6 %tmp.1912 = icmp ugt i64 %tmp.1710, 0 ; <i1> [#uses=1]
|
| udiv-simplify-bug-0.ll | 1 ; RUN: opt < %s -instcombine -S | grep "ret i64 0" | count 2
3 define i64 @foo(i32 %x) nounwind {
6 %z = sext i32 %r to i64
7 ret i64 %z
9 define i64 @bar(i32 %x) nounwind {
12 %z = sext i32 %r to i64
13 ret i64 %z
|
| /external/clang/test/CodeGenCXX/ |
| debug-info-dup-fwd-decl.cpp | 22 // CHECK: metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata {{.*}} [ DW_TAG_pointer_type ]
23 // CHECK: metadata !"data", metadata !{{.*}}, i32 14, i64 32, i64 32, i32 0, i32 0
24 // CHECK-NOT: metadata !"data", metadata {{.*}}, i32 14, i64 0, i64 0, i32 0, i32 4,
|
| debug-info-zero-length-arrays.cpp | 9 // CHECK: !{{.*}} = metadata !{i32 {{.*}}, metadata {{.*}}, metadata !"x", metadata {{.*}}, i32 5, i64 0, i64 0, i64 0, i32 1, metadata [[ARRAY_TYPE:.*]]} ; [ DW_TAG_member ]
10 // CHECK: [[ARRAY_TYPE]] = metadata !{i32 {{.*}}, null, metadata !"", null, i32 0, i64 0, i64 32, i32 0, i32 0, metadata [[BASE_TYPE:.*]], metadata [[ELEM_TYPE:.*]], i32 0, i32 0} ; [ DW_TAG_array_type ]
11 // CHECK: [[BASE_TYPE]] = metadata !{i32 {{.*}}, null, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
13 // CHECK: [[SUBRANGE]] = metadata !{i32 786465, i64 0, i64 -1} ; [ DW_TAG_subrange_type ] [unbounded
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| smml.ll | 5 %conv4 = zext i32 %a to i64
6 %conv1 = sext i32 %b to i64
7 %conv2 = sext i32 %c to i64
8 %mul = mul nsw i64 %conv2, %conv1
9 %shr5 = lshr i64 %mul, 32
10 %sub = sub nsw i64 %conv4, %shr5
11 %conv3 = trunc i64 %sub to i32
|
| 2009-09-27-CoalescerBug.ll | 8 define arm_aapcs_vfpcc i64 @__fixsfdi(float %a) nounwind {
15 %2 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %1) nounwind ; <i64> [#uses=1]
16 %3 = sub i64 0, %2 ; <i64> [#uses=1]
17 ret i64 %3
20 %4 = tail call arm_aapcs_vfpcc i64 @__fixunssfdi(float %a) nounwind ; <i64> [#uses=1]
21 ret i64 %4
24 declare arm_aapcs_vfpcc i64 @__fixunssfdi(float
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| multiple-return-values-cross-block-with-invoke.ll | 3 declare { i64, double } @wild()
5 define void @foo(i64* %p, double* %q) nounwind {
6 %t = invoke { i64, double } @wild() to label %normal unwind label %handler
9 %mrv_gr = extractvalue { i64, double } %t, 0
10 store i64 %mrv_gr, i64* %p
11 %mrv_gr12681 = extractvalue { i64, double } %t, 1
|
| /external/llvm/test/CodeGen/PowerPC/ |
| int-fp-conv-1.ll | 4 define i64 @__fixunstfdi(ppc_fp128 %a) nounwind {
6 %tmp1213 = uitofp i64 0 to ppc_fp128 ; <ppc_fp128> [#uses=1]
9 %tmp282930 = zext i32 %tmp2829 to i64 ; <i64> [#uses=1]
10 %tmp32 = add i64 %tmp282930, 0 ; <i64> [#uses=1]
11 ret i64 %tmp32
|
| /external/llvm/test/ExecutionEngine/MCJIT/ |
| test-shift.ll | 11 %t2.s.upgrd.3 = shl i64 1, 4 ; <i64> [#uses=0]
12 %t2.upgrd.4 = shl i64 1, 5 ; <i64> [#uses=0]
19 %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
21 %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0
[all...] |
| /external/llvm/test/ExecutionEngine/ |
| test-shift.ll | 11 %t2.s.upgrd.3 = shl i64 1, 4 ; <i64> [#uses=0]
12 %t2.upgrd.4 = shl i64 1, 5 ; <i64> [#uses=0]
19 %tr1.l = ashr i64 1, 4 ; <i64> [#uses=0]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
21 %tr2.l = ashr i64 1, %shift.upgrd.7 ; <i64> [#uses=0
[all...] |
| /external/llvm/test/Transforms/GlobalOpt/ |
| globalsra-unknown-index.ll | 15 store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 ptrtoint (i8* @addr to i64)), align 4
18 define i32 @borf(i64 %i, i64 %j) {
19 %p = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0
21 %q = getelementptr inbounds [3 x %struct.X]* @Y, i64 0, i64 0, i32 1, i64
[all...] |
