| /external/llvm/test/Transforms/InstCombine/ |
| 2003-05-27-ConstExprCrash.ll | 5 define i64 @test() {
6 %C = add i64 1, 2 ; <i64> [#uses=1]
7 %V = add i64 ptrtoint (i32* @X to i64), %C ; <i64> [#uses=1]
8 ret i64 %V
|
| srem.ll | 3 define i64 @foo(i64 %x1, i64 %y2) {
4 %r = sdiv i64 %x1, %y2
5 %r7 = mul i64 %r, %y2
6 %r8 = sub i64 %x1, %r7
7 ret i64 %r8
|
| urem.ll | 3 define i64 @rem_unsigned(i64 %x1, i64 %y2) {
4 %r = udiv i64 %x1, %y2
5 %r7 = mul i64 %r, %y2
6 %r8 = sub i64 %x1, %r7
7 ret i64 %r8
|
| constant-fold-gep.ll | 2 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64"
12 ; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 16
13 store i32 1, i32* getelementptr ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 0), align 4
14 ; CHECK: store i32 1, i32* getelementptr inbounds ([3 x %struct.X]* @Y, i64 0, i64 0, i32 0, i64 1), align
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| inline-asm-2addr.ll | 3 define i64 @t(i64 %a, i64 %b) nounwind ssp {
5 %asmtmp = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %a) nounwind ; <i64> [#uses=1]
6 %asmtmp1 = tail call i64 asm "rorq $1,$0", "=r,J,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i32 1, i64 %b) nounwind ; <i64> [#uses=1]
7 %0 = add i64 %asmtmp1, %asmtmp ; <i64> [#uses=1
[all...] |
| sse42_64.ll | 3 declare i64 @llvm.x86.sse42.crc32.64.8(i64, i8) nounwind
4 declare i64 @llvm.x86.sse42.crc32.64.64(i64, i64) nounwind
6 define i64 @crc32_64_8(i64 %a, i8 %b) nounwind {
7 %tmp = call i64 @llvm.x86.sse42.crc32.64.8(i64 %a, i8 %b)
8 ret i64 %tm
[all...] |
| 2009-06-02-RewriterBug.ll | 4 define void @sha256_block1(i32* nocapture %arr, i8* nocapture %in, i64 %num) nounwind {
12 %indvar2787 = phi i64 [ 0, %bb.nph ], [ %indvar.next2788, %for.end ] ; <i64> [#uses=2]
13 %tmp2791 = mul i64 %indvar2787, 44 ; <i64> [#uses=0]
14 %ctg22996 = getelementptr i8* %in, i64 0 ; <i8*> [#uses=1]
15 %conv = zext i32 undef to i64 ; <i64> [#uses=1]
16 %conv11 = zext i32 undef to i64 ; <i64> [#uses=1
[all...] |
| 2009-04-16-SpillerUnfold.ll | 6 %struct.SHA512_CTX = type { [8 x i64], i64, i64, %struct.anon, i32, i32 }
7 %struct.anon = type { [16 x i64] }
8 @K512 = external constant [80 x i64], align 32 ; <[80 x i64]*> [#uses=2]
10 define fastcc void @sha512_block_data_order(%struct.SHA512_CTX* nocapture %ctx, i8* nocapture %in, i64 %num) nounwind ssp {
15 %e.0489 = phi i64 [ 0, %entry ], [ %e.0, %bb349 ] ; <i64> [#uses=3]
16 %b.0472 = phi i64 [ 0, %entry ], [ %87, %bb349 ] ; <i64> [#uses=2
[all...] |
| inline-asm-tied.ll | 7 @llvm.used = appending global [1 x i8*] [i8* bitcast (i64 (i64)* @_OSSwapInt64 to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
9 define i64 @_OSSwapInt64(i64 %_data) nounwind {
11 %retval = alloca i64 ; <i64*> [#uses=2]
12 %_data.addr = alloca i64 ; <i64*> [#uses=4]
13 store i64 %_data, i64* %_data.add
[all...] |
| 2007-10-31-extractelement-i64.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
6 define <1 x i64> @a(<2 x i64> %__A) {
8 %__A_addr = alloca <2 x i64> ; <<2 x i64>*> [#uses=2]
9 %retval = alloca <1 x i64>, align 8 ; <<1 x i64>*> [#uses=3]
11 store <2 x i64> %__A, <2 x i64>* %__A_addr
12 %tmp = load <2 x i64>* %__A_addr, align 16 ; <<2 x i64>> [#uses=1
[all...] |
| h-registers-1.ll | 10 define i64 @foo(i64 %a, i64 %b, i64 %c, i64 %d,
11 i64 %e, i64 %f, i64 %g, i64 %h) {
12 %sa = lshr i64 %a,
[all...] |
| 2006-07-10-InlineAsmAConstraint.ll | 4 define i64 @test() {
5 %tmp.i5 = call i64 asm sideeffect "rdtsc", "=A,~{dirflag},~{fpsr},~{flags}"( ) ; <i64> [#uses=1]
6 ret i64 %tmp.i5
|
| 2007-11-04-LiveVariablesBug.ll | 4 define void @xor_sse_2(i64 %bytes, i64* %p1, i64* %p2) {
6 %p2_addr = alloca i64* ; <i64**> [#uses=2]
8 store i64* %p2, i64** %p2_addr, align 8
9 %tmp1 = lshr i64 %bytes, 8 ; <i64> [#uses=1]
10 %tmp12 = trunc i64 %tmp1 to i32 ; <i32> [#uses=2
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| long.ll | 3 define i64 @f1() {
6 ret i64 0
9 define i64 @f2() {
12 ret i64 1
15 define i64 @f3() {
19 ret i64 2147483647
22 define i64 @f4() {
26 ret i64 2147483648
29 define i64 @f5() {
34 ret i64 922337203685477580
[all...] |
| 2007-04-30-CombinerCrash.ll | 3 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:64"
5 %struct.CHESS_POSITION = type { i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i64, i32, i32, i8, i8, [64 x i8], i8, i8, i8, i8, i8
[all...] |
| formal.ll | 3 declare void @bar(i64 %x, i64 %y)
6 call void @bar(i64 2, i64 3)
|
| ret_i64_arg_split.ll | 3 define i64 @test_i64_arg_split(i64 %a1, i32 %a2, i64 %a3) {
4 ret i64 %a3
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64shift.ll | 3 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
6 %shl = shl i64 %a0, %a1
7 ret i64 %shl
10 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
13 %shr = ashr i64 %a0, %a1
14 ret i64 %sh
[all...] |
| /external/llvm/test/Transforms/GVN/ |
| 2011-07-07-MatchIntrinsicExtract.ll | 4 %0 = type { i64, i1 }
6 define i64 @test1(i64 %a, i64 %b) nounwind ssp {
8 %uadd = tail call %0 @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
10 %add1 = add i64 %a, %b
11 ret i64 %add1
18 define i64 @test2(i64 %a, i64 %b) nounwind ssp
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-sbc.ll | 3 define i64 @f1(i64 %a, i64 %b) {
6 %tmp = sub i64 %a, %b
7 ret i64 %tmp
11 define i64 @f2(i64 %a) {
15 %tmp = sub i64 %a, 734439407618
16 ret i64 %tmp
20 define i64 @f3(i64 %a)
[all...] |
| thumb2-adc.ll | 4 define i64 @f1(i64 %a) {
7 %tmp = add i64 %a, 734439407618
8 ret i64 %tmp
12 define i64 @f2(i64 %a) {
15 %tmp = add i64 %a, 5066626890203138
16 ret i64 %tmp
20 define i64 @f3(i64 %a)
[all...] |
| /external/llvm/test/CodeGen/Generic/ |
| 2008-02-04-Ctlz.ll | 5 define i32 @main(i64 %arg) nounwind {
7 %tmp37 = tail call i64 @llvm.ctlz.i64( i64 %arg, i1 true ) ; <i64> [#uses=1]
8 %tmp47 = tail call i64 @llvm.cttz.i64( i64 %arg, i1 true ) ; <i64> [#uses=1]
9 %tmp57 = tail call i64 @llvm.ctpop.i64( i64 %arg ) ; <i64> [#uses=1
[all...] |
| /external/llvm/test/CodeGen/PowerPC/ |
| atomic-2.ll | 3 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
6 %tmp = atomicrmw add i64* %mem, i64 %val monotonic
8 ret i64 %tmp
11 define i64 @exchange_and_cmp(i64* %mem) nounwind {
14 %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotoni
[all...] |
| subc.ll | 9 define i64 @sub_ll(i64 %a, i64 %b) {
11 %tmp.2 = sub i64 %a, %b ; <i64> [#uses=1]
12 ret i64 %tmp.2
15 define i64 @sub_l_5(i64 %a) {
17 %tmp.1 = sub i64 5, %a ; <i64> [#uses=1
[all...] |
| /external/llvm/test/Assembler/ |
| vector-shift.ll | 30 ; CHECK: ret <2 x i64> <i64 40, i64 192>
31 define <2 x i64> @foo_ce() nounwind {
32 ret <2 x i64> shl (<2 x i64> <i64 5, i64 6>, <2 x i64> <i64 3, i64 5>
[all...] |
