/external/v8/src/mips/ |
disasm-mips.cc | 675 case MULTU: 676 Format(instr, "multu 'rs, 'rt");
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constants-mips.h | 321 MULTU = ((3 << 3) + 1),
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assembler-mips.cc | 1224 void Assembler::multu(Register rs, Register rt) { function in class:v8::Assembler [all...] |
assembler-mips.h | 710 void multu(Register rs, Register rt); [all...] |
simulator-mips.cc | [all...] |
macro-assembler-mips.cc | 609 void MacroAssembler::Multu(Register rs, const Operand& rt) { 611 multu(rs, rt.rm()); 616 multu(rs, at); [all...] |
macro-assembler-mips.h | 571 DEFINE_INSTRUCTION2(Multu); [all...] |
/external/llvm/lib/Target/Mips/ |
Mips16InstrInfo.td | 816 def MultuRxRy16: FMULT16_ins<"multu", IIAlu> { 834 // Format: MULTU rx, ry MIPS16e 838 def MultuRxRyRz16: FMULT16_LO_ins<"multu", IIAlu> { [all...] |
MipsDSPInstrInfo.td | 71 def MipsMULTU : MipsDSPBase<"MULTU", SDT_MipsDPA>; [all...] |
MipsInstrInfo.td | [all...] |
MipsISelLowering.cpp | 190 case MipsISD::MULTU: return "MipsISD::MULTU"; [all...] |
/external/llvm/test/CodeGen/Mips/ |
dsp-r1.ll | 353 ; CHECK: multu $ac{{[0-9]}} 355 %0 = tail call i64 @llvm.mips.multu(i32 %a0, i32 %a1) 359 declare i64 @llvm.mips.multu(i32, i32) nounwind readnone [all...] |
/external/clang/test/CodeGen/ |
builtins-mips.c | 208 // CHECK: call i64 @llvm.mips.multu
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/system/core/libpixelflinger/codeflinger/ |
MIPSAssembler.h | 279 void MULTU(int Rs, int Rt); // dest is hi,lo
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mips_disassem.c | 83 /*24 */ "mult", "multu","div", "divu", "dmult","dmultu","ddiv","ddivu",
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MIPSAssembler.cpp | [all...] |
/external/valgrind/main/VEX/priv/ |
guest_mips_toIR.c | [all...] |
host_mips_defs.c | [all...] |
/prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.6/bin/ |
mipsel-linux-android-as | |
mipsel-linux-android-objdump | |
mipsel-linux-android-run | |
/prebuilts/gcc/linux-x86/mips/mipsel-linux-android-4.6/mipsel-linux-android/bin/ |
as | |
objdump | |
/external/qemu/ |
mips-dis.c | [all...] |
/dalvik/vm/compiler/template/out/ |
CompilerTemplateAsm-mips.S | [all...] |