| /external/valgrind/main/none/tests/s390x/ |
| cu24_1.c | 69 "srl %2,28\n\t"
|
| cu42.c | 72 "srl %2,28\n\t"
|
| cu21.c | 82 "srl %2,28\n\t"
|
| cu21_1.c | 82 "srl %2,28\n\t"
|
| cu41.c | 83 "srl %2,28\n\t"
|
| mvcl.c | 42 "srl %0,28\n\t"
|
| /external/llvm/lib/Target/X86/ |
| X86InstrCompiler.td | [all...] |
| X86ISelDAGToDAG.cpp | 772 if (Shift.getOpcode() != ISD::SRL ||
786 SDValue Srl = DAG.getNode(ISD::SRL, DL, VT, X, Eight);
787 SDValue And = DAG.getNode(ISD::AND, DL, VT, Srl, NewMask);
797 InsertDAGNode(DAG, N, Srl);
853 // scale. Patterns such as (shl (srl x, c1), c2) are canonicalized into (and
854 // (srl x, SHIFT), MASK) by DAGCombines that don't know the shl can be done i
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 347 // Look for (add X1, (and (srl X2, c1), c2)) where c2 is constant with
351 // (add X1, (shl (and (srl X2, c1), (c2>>tz)), tz)) where tz is the number
353 // operand of 'add' and the 'and' and 'srl' would become a bits extraction
383 // Look for (and (srl X, c1), c2).
384 SDValue Srl = N1.getOperand(0);
386 if (!isOpcWithIntImmediate(Srl.getNode(), ISD::SRL, Srl_imm) ||
405 Srl = CurDAG->getNode(ISD::SRL, Srl.getDebugLoc(), MVT::i32
[all...] |
| ARMISelLowering.h | 76 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
78 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 398 case LSR: mMips->SRL(tmpReg, amode.reg, amode.value); break;
509 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
541 case LSR: mMips->SRL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/v8/src/mips/ |
| macro-assembler-mips.cc | 435 srl(at, reg0, 12);
443 srl(at, reg0, 4);
453 srl(at, reg0, 16);
761 srl(rd, rs, 0);
763 srl(at, rs, rt.imm32_);
944 srl(rt, rt, shift_right);
963 srl(at, at, 32 - size);
[all...] |
| stub-cache-mips.cc | 226 __ srl(scratch, scratch, kHeapObjectTagSize);
243 __ srl(at, name, kHeapObjectTagSize);
[all...] |
| /external/openssl/crypto/bn/asm/ |
| bn-mips.S | 642 srl $1,$5,$13
651 srl $3,$6,4*4 # bits
659 srl $9,$4,4*4 # bits
660 srl $8,4*4 # q=0xffffffff
667 srl $1,$5,4*4 # bits
692 srl $9,$4,4*4 # bits
693 srl $8,4*4 # q=0xffffffff
700 srl $1,$5,4*4 # bits
722 srl $3,$4,$25 # $3 contains remainder if anybody wants it
723 srl $6,$25 # restore $
[all...] |
| /external/icu4c/config/ |
| icu-config.1.in | 8 .\" Modified by Steven R. Loomis <srl@jtcsv.com>.
|
| /external/icu4c/samples/date/ |
| date.c | 14 * 08/11/11 srl added Parse and milli/second in/out
|
| /external/icu4c/test/intltest/ |
| dadrfmt.cpp | 10 * 07/09/2007 srl Copied from dadrcoll.cpp
|
| /external/icu4c/tools/ |
| icu-svnprops-check.py | 80 # new additions 2007-dec-5 srl
|
| /external/valgrind/main/helgrind/tests/ |
| annotate_hbefore.c | 181 "srl %0,28\n\t"
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGDumper.cpp | 174 case ISD::SRL: return "srl";
|
| /external/llvm/lib/Target/Mips/ |
| Mips64InstrInfo.td | 105 def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
110 def DSRLV : shift_rotate_reg<"dsrlv", CPU64RegsOpnd, srl>, SRLV_FM<0x16, 0>;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrAltivec.td | [all...] |
| /external/llvm/lib/Target/R600/ |
| R600ISelLowering.cpp | 681 return DAG.getNode(ISD::SRL, Ptr.getDebugLoc(), Ptr.getValueType(), Ptr,
725 DAG.getNode(ISD::SRL, DL, Ptr.getValueType(),
854 DAG.getNode(ISD::SRL, DL, MVT::i32, Ptr, DAG.getConstant(4, MVT::i32)),
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcInstrInfo.td | 455 defm SRL : F3_12<"srl", 0b100110, srl>;
[all...] |
| /external/aac/libFDK/src/arm/ |
| fft_rad2_arm.cpp | 103 date: 28.07.2005 srl
|
