| /external/icu4c/common/ |
| umutex.cpp | 15 * 04/07/99 srl updated
|
| /external/icu4c/i18n/ |
| japancal.cpp | 10 * 05/16/2003 srl copied from buddhcal.cpp
|
| tblcoll.cpp | 51 * 11/17/99 srl More performance enhancements. Inlined some internal functions.
|
| /external/icu4c/test/intltest/ |
| dadrcal.cpp | 10 * 07/09/2007 srl Copied from dadrcoll.cpp
|
| /external/libffi/src/mips/ |
| o32.S | 80 SRL t2, t0, 4 # shift our arg info
|
| /external/llvm/docs/TableGen/ |
| LangRef.rst | 94 :!add !shl !sra !srl
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/TableGen/ |
| TGLexer.cpp | 476 .Case("srl", tgtok::XSRL)
|
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.td | 1171 // Format: SRL rx, ry, sa MIPS16e
1176 def SrlX16: FEXT_SHIFT16_ins<0b10, "srl", IIAlu>;
[all...] |
| MipsInstrInfo.td | 830 def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
835 def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
[all...] |
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 363 # CHECK: srl $4, $3, 7
|
| mips32_le.txt | 363 # CHECK: srl $4, $3, 7
|
| mips32r2.txt | 384 # CHECK: srl $4, $3, 7
|
| mips32r2_le.txt | 384 # CHECK: srl $4, $3, 7
|
| /external/openssl/crypto/modes/asm/ |
| ghash-sparcv9.pl | 191 srl $Zlo,8,$xi1
|
| /external/openssl/crypto/sha/asm/ |
| sha512-s390x.pl | 91 $SHR="srl"; # logical right shift
|
| /external/v8/src/mips/ |
| debug-mips.cc | 168 __ srl(reg, reg, kSmiTagSize);
|
| disasm-mips.cc | 635 case SRL:
637 Format(instr, "srl 'rd, 'rt, 'sa");
|
| /external/valgrind/main/coregrind/m_dispatch/ |
| dispatch-mips32-linux.S | 194 srl $14, $14, 2
|
| /dalvik/vm/compiler/template/out/ |
| CompilerTemplateAsm-mips.S | 217 #define GET_OPA(rd) srl rd, rINST, 8
223 #define GET_OPB(rd) srl rd, rINST, 12
256 srl AT, roff, rshift; \
[all...] |
| /external/jpeg/ |
| config.guess | 71 srl \$1,8,\$2
523 srl \$1,8,\$2
|
| /external/qemu/distrib/jpeg-6b/ |
| config.guess | 71 srl \$1,8,\$2
523 srl \$1,8,\$2
|
| /external/valgrind/main/VEX/priv/ |
| guest_mips_toIR.c | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | 498 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86)
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.cpp | 130 setOperationAction(ISD::SRL, VT, Custom);
585 setTargetDAGCombine(ISD::SRL);
652 setOperationAction(ISD::SRL, MVT::i64, Custom);
[all...] |
