/external/llvm/lib/Target/AArch64/ |
AArch64ISelLowering.cpp | 350 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 357 BuildMI(BB, dl, TII->get(BinOpcode), scratch) 360 BuildMI(BB, dl, TII->get(BinOpcode), scratch) 368 BuildMI(BB, dl, TII->get(strOpc), stxr_status).addReg(scratch).addReg(ptr); 369 BuildMI(BB, dl, TII->get(AArch64::CBNZw)) 443 BuildMI(BB, dl, TII->get(ldrOpc), dest).addReg(ptr); 447 BuildMI(BB, dl, TII->get(CmpOp)) 450 BuildMI(BB, dl, TII->get(Size == 8 ? AArch64::CSELxxxc : AArch64::CSELwwwc), 457 BuildMI(BB, dl, TII->get(strOpc), stxr_status) 459 BuildMI(BB, dl, TII->get(AArch64::CBNZw) [all...] |
/external/llvm/lib/Target/R600/ |
R600InstrInfo.cpp | 318 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(TBB); 326 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND)) 336 BuildMI(&MBB, DL, get(AMDGPU::JUMP_COND)) 339 BuildMI(&MBB, DL, get(AMDGPU::JUMP)).addMBB(FBB); 655 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
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R600ExpandSpecialInstrs.cpp | 100 BuildMI(MBB, I, MBB.findDebugLoc(I),
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SIInsertWaits.cpp | 290 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
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/external/llvm/lib/Target/ARM/ |
MLxExpansionPass.cpp | 292 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg) 299 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
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Thumb2ITBlockPass.cpp | 181 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
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Thumb2SizeReduction.cpp | 467 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc)); 528 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), 691 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); 788 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID); [all...] |
ARMBaseRegisterInfo.cpp | 377 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp)) 558 MachineInstrBuilder MIB = AddDefaultPred(BuildMI(*MBB, Ins, DL, MCID, BaseReg)
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/external/llvm/lib/Target/Hexagon/ |
HexagonNewValueJump.cpp | 608 NewMI = BuildMI(*MBB, jmpPos, dl, 615 NewMI = BuildMI(*MBB, jmpPos, dl,
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/external/llvm/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 235 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE); 236 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE), 238 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE); 252 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE); 271 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR)); 272 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg); 275 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8)); 276 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg); [all...] |
/external/llvm/lib/Target/X86/ |
X86ISelLowering.cpp | [all...] |
/external/llvm/lib/Target/MBlaze/ |
MBlazeDelaySlotFiller.cpp | 242 BuildMI(MBB, ++J, I->getDebugLoc(), TII->get(MBlaze::NOP));
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/external/llvm/lib/CodeGen/ |
MachineInstrBundle.cpp | 110 MachineInstrBuilder MIB = BuildMI(*MBB.getParent(), FirstMI->getDebugLoc(),
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MachineRegisterInfo.cpp | 324 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
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MachineSSAUpdater.cpp | 118 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
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TailDuplication.cpp | 827 Copies.push_back(BuildMI(*PredBB, Loc, DebugLoc(), 888 Copies.push_back(BuildMI(*PrevBB, Loc, DebugLoc(), [all...] |
GCStrategy.cpp | 357 BuildMI(MBB, MI, DL, TII->get(TargetOpcode::GC_LABEL)).addSym(Label);
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PeepholeOptimizer.cpp | 284 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc(),
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StrongPHIElimination.cpp | 695 MachineInstr *CopyInstr = BuildMI(*PredBB, 764 MachineInstr *CopyInstr = BuildMI(*MBB,
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TwoAddressInstructionPass.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ScheduleDAGSDNodes.cpp | 778 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg) 787 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase) [all...] |
FunctionLoweringInfo.cpp | 176 BuildMI(MBB, DL, TII->get(TargetOpcode::PHI), PHIReg + i);
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SelectionDAGISel.cpp | 419 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 440 BuildMI(*MF, CopyUseMI->getDebugLoc(), 818 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) [all...] |
/external/llvm/lib/Target/Mips/ |
MipsDelaySlotFiller.cpp | 517 BuildMI(MBB, llvm::next(I), I->getDebugLoc(), TII->get(Mips::NOP));
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/external/llvm/lib/Target/Sparc/ |
SparcISelLowering.cpp | [all...] |