/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
omxVCM4P2_MCReconBlock_s.s | 678 UXTB16 tmp2, dst, ROR #8 ;// tmp2 = [0d0b] 691 UXTB16 tmp2, dst, ROR #8
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/external/v8/src/arm/ |
constants-arm.h | 290 ROR = 3 << 5, // Rotate right. 292 // RRX is encoded as ROR with shift_imm == 0. 295 // detect it and emit the correct ROR shift operand with shift_imm == 0.
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disasm-arm.cc | 204 "lsl", "lsr", "asr", "ror" 224 if ((shift == ROR) && (shift_amount == 0)) { [all...] |
simulator-arm.cc | [all...] |
assembler-arm.cc | 185 ASSERT(shift_op != ROR || shift_imm != 0); // use RRX if you mean it 191 // encoded as ROR with shift_imm == 0 193 shift_op_ = ROR; [all...] |
/frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.s | 441 UXTB16 PredVal2,PredVal,ROR #8 ;// PredVal2 = [0d0b]
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/external/llvm/lib/Target/AArch64/InstPrinter/ |
AArch64InstPrinter.cpp | 269 case A64SE::ROR: O << "ror"; break;
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/system/core/libpixelflinger/codeflinger/ |
ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR
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MIPSAssembler.cpp | 400 case ROR: if (mips32r2) { 511 case ROR: if (mips32r2) { 543 case ROR: if (mips32r2) { [all...] |
ARMAssembler.cpp | 517 return (ROR<<5) | (Rm&0xF);
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GGLAssembler.cpp | 209 reg_imm(parts.count.reg, ROR, GGL_DITHER_ORDER_SHIFT)); 213 reg_imm(parts.count.reg, ROR, 32 - GGL_DITHER_ORDER_SHIFT)); [all...] |
/external/llvm/lib/Target/AArch64/Utils/ |
AArch64BaseInfo.h | 294 ROR,
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/external/llvm/test/MC/ARM/ |
basic-thumb-instructions.s | 457 @ ROR
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basic-thumb2-instructions.s | 47 adc r0, r1, r3, ror #4 57 @ CHECK: adc.w r0, r1, r3, ror #4 @ encoding: [0x41,0xeb,0x33,0x10] 119 add.w r4, r8, r1, ror #12 127 @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34] 165 and.w r9, r12, r1, ror #17 171 @ CHECK: and.w r9, r12, r1, ror #17 @ encoding: [0x0c,0xea,0x71,0x49] 263 bic r5, r6, r8, ror #1 272 bic r12, r6, ror #29 280 @ CHECK: bic.w r5, r6, r8, ror #1 @ encoding: [0x26,0xea,0x78,0x05] 288 @ CHECK: bic.w r12, r12, r6, ror #29 @ encoding: [0x2c,0xea,0x76,0x7c [all...] |
basic-arm-instructions.s | 58 adc r4, r5, r6, ror #1 59 adc r4, r5, r6, ror #31 65 adc r6, r7, r8, ror r9 78 adc r4, r5, ror #1 79 adc r4, r5, ror #31 84 adc r6, r7, ror r9 97 @ CHECK: adc r4, r5, r6, ror #1 @ encoding: [0xe6,0x40,0xa5,0xe0] 98 @ CHECK: adc r4, r5, r6, ror #31 @ encoding: [0xe6,0x4f,0xa5,0xe0] 103 @ CHECK: adc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xa7,0xe0] 115 @ CHECK: adc r4, r4, r5, ror #1 @ encoding: [0xe5,0x40,0xa4,0xe0 [all...] |
/external/llvm/lib/Target/AArch64/AsmParser/ |
AArch64AsmParser.cpp | [all...] |
/dalvik/vm/compiler/codegen/x86/libenc/ |
enc_tabl.cpp | [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
DAGCombiner.cpp | [all...] |
/external/dropbear/libtomcrypt/ |
crypt.tex | 297 \index{ROL} \index{ROR} \index{ROL64} \index{ROR64} \index{ROLc} \index{RORc} \index{ROL64c} \index{ROR64c} 304 \hline ROR(x, y) & {\bf unsigned long} x, {\bf unsigned long} y & $x >> y, 0 \le y \le 31$ \\ [all...] |
/build/tools/droiddoc/templates-sac/assets/js/ |
android_3p-bundle.js | [all...] |
/build/tools/droiddoc/templates-sdk/assets/js/ |
android_3p-bundle.js | [all...] |