| /prebuilts/gcc/darwin-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 80 tree op2; member in struct:vn_reference_op_struct
|
| /prebuilts/gcc/linux-x86/arm/arm-eabi-4.6/lib/gcc/arm-eabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 80 tree op2; member in struct:vn_reference_op_struct
|
| /prebuilts/gcc/linux-x86/arm/arm-linux-androideabi-4.6/lib/gcc/arm-linux-androideabi/4.6.x-google/plugin/include/ |
| tree-ssa-sccvn.h | 80 tree op2; member in struct:vn_reference_op_struct
|
| /dalvik/vm/compiler/codegen/x86/libenc/ |
| enc_base.h | 546 Operands(const Operand& op0, const Operand& op1, const Operand& op2)
549 add(op0); add(op1); add(op2);
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MacroAssembler.h | 113 void branch32(Condition cond, RegisterID op1, RegisterID op2, Label target)
115 branch32(cond, op1, op2).linkTo(target, this);
|
| ARMv7Assembler.h | [all...] |
| /external/javassist/src/main/javassist/compiler/ |
| CodeGen.java | 1414 int op, op2; local
[all...] |
| Parser.java | 417 int op2 = s2.getOperator(); local
418 if (op2 == CASE || op2 == DEFAULT) {
[all...] |
| /external/aac/libFDK/include/ |
| fixpoint_math.h | 253 const FIXP_SGL op2);
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGJITCodeGenerator.h | 324 void bitOp(NodeType op, MacroAssembler::RegisterID op1, MacroAssembler::RegisterID op2, MacroAssembler::RegisterID result)
328 m_jit.and32(op1, op2, result);
331 m_jit.or32(op1, op2, result);
334 m_jit.xor32(op1, op2, result);
[all...] |
| /external/webkit/Source/JavaScriptCore/jit/ |
| JITInlineMethods.h | 617 ALWAYS_INLINE bool JIT::getOperandConstantImmediateInt(unsigned op1, unsigned op2, unsigned& op, int32_t& constant)
621 op = op2;
625 if (isOperandConstantImmediateInt(op2)) {
626 constant = getConstantOperand(op2).asInt32();
|
| JITOpcodes32_64.cpp | 506 unsigned op2 = currentInstruction[2].u.operand; local
512 emitLoad(op2, regT1, regT0);
518 if (isOperandConstantImmediateInt(op2)) {
521 addJump(branch32(LessThanOrEqual, regT0, Imm32(getConstantOperand(op2).asInt32())), target);
525 emitLoad2(op1, regT1, regT0, op2, regT3, regT2);
534 unsigned op2 = currentInstruction[2].u.operand; local
537 if (!isOperandConstantImmediateInt(op1) && !isOperandConstantImmediateInt(op2))
543 stubCall.addArgument(op2);
1058 unsigned op2 = currentInstruction[3].u.operand; local
[all...] |
| JITOpcodes.cpp | 351 unsigned op2 = currentInstruction[2].u.operand; local
353 if (isOperandConstantImmediateInt(op2)) {
356 int32_t op2imm = getConstantOperandImmediateInt(op2);
359 emitGetVirtualRegisters(op1, regT0, op2, regT1);
1341 unsigned op2 = currentInstruction[2].u.operand; local
[all...] |
| /ndk/sources/host-tools/nawk-20071023/ |
| parse.c | 141 Node *op2(int a, Node *b, Node *c) function
|
| proto.h | 82 extern Node *op2(int, Node *, Node *);
|
| /external/aac/libFDK/src/ |
| fixpoint_math.cpp | 216 FIXP_DBL mul_dbl_sgl_rnd (const FIXP_DBL op1, const FIXP_SGL op2)
220 SHORT u = (SHORT)(op2);
442 description: delivers op1/op2 with op3-bit accuracy
|
| /external/valgrind/main/VEX/test/ |
| test-amd64.c | 932 uint64_t op0, op1, op2;
941 op2 = 0x6532432432434;
946 : "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
[all...] |
| test-i386.c | 894 uint64_t op0, op1, op2;
903 op2 = 0x6532432432434;
908 : "0" (op0), "m" (op1), "b" ((int)op2), "c" ((int)(op2 >> 32)));
[all...] |
| /hardware/qcom/msm8960/kernel-headers/linux/ |
| msm_kgsl.h | 332 unsigned int op2; member in struct:kgsl_cff_user_event
|
| /hardware/qcom/msm8960/original-kernel-headers/linux/ |
| msm_kgsl.h | 423 unsigned int op2; member in struct:kgsl_cff_user_event
|
| /external/qemu/target-arm/ |
| neon_helper.c | 1014 uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2)
1029 result ^= op2 & mask;
1031 op2 = (op2 << 1) & 0xfefefefe;
1036 uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2)
1040 uint64_t op2ex = op2;
[all...] |
| translate.c | 517 switch (op2) { \
525 static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
572 static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
576 switch (op2) {
6083 int op2 = (insn >> 5) & 7; local
6143 int op2 = (insn >> 5) & 7; local
8727 int op2 = (insn >> 6) & 0x3f; local
[all...] |
| /external/valgrind/main/VEX/priv/ |
| guest_s390_helpers.c | 856 opcode " %[op1],%[op2]\n\t" \
858 : [op2] "d"(cc_dep2) \
871 opcode " %[op1],%[op2]\n\t" /* then redo the op */\
873 : [op2] "d"(cc_dep2), [op3] "d"(cc_ndep) \
886 opcode " %[op1],%[op2]\n\t" /* then redo the op */\
888 : [op2] "d"(cc_dep2), [op3] "d"(cc_ndep) \
[all...] |
| /external/qemu/tcg/ppc64/ |
| tcg-target.c | 530 int offset, int op1, int op2)
536 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
541 int offset, int op1, int op2)
547 tcg_out32 (s, op2 | RT (ret) | RA (addr) | RB (0));
[all...] |
| /external/qemu/target-i386/ |
| translate.c | [all...] |
