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    Searched full:getinstr (Results 1 - 15 of 15) sorted by null

  /external/llvm/lib/Target/ARM/
ARMHazardRecognizer.cpp 38 MachineInstr *MI = SU->getInstr();
80 MachineInstr *MI = SU->getInstr();
  /external/llvm/lib/Target/R600/
R600MachineScheduler.cpp 143 for (MachineInstr::mop_iterator It = SU->getInstr()->operands_begin(),
144 E = SU->getInstr()->operands_end(); It != E; ++It) {
186 MachineInstr *MI = SU->getInstr();
247 int Opcode = SU->getInstr()->getOpcode();
296 InstructionsGroupCandidate.push_back(SU->getInstr());
362 AssignSlot(UnslotedSU->getInstr(), Slot);
371 AssignSlot(UnslotedSU->getInstr(), Slot);
404 InstructionsGroupCandidate.push_back(SU->getInstr());
  /external/llvm/lib/Target/Hexagon/
HexagonMachineScheduler.cpp 30 if (SUnits[su].getInstr()->isCall())
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
44 if (!SU || !SU->getInstr())
49 switch (SU->getInstr()->getOpcode()) {
51 if (!ResourcesModel->canReserveResources(SU->getInstr()))
101 switch (SU->getInstr()->getOpcode()) {
103 ResourcesModel->reserveResources(SU->getInstr());
124 DEBUG(Packet[i]->getInstr()->dump());
240 assert(SU->getInstr() && "Scheduled SUnit must have instr");
272 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
    [all...]
HexagonVLIWPacketizer.cpp     [all...]
  /external/llvm/lib/CodeGen/
ScheduleDAGInstrs.cpp 242 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx);
266 RegUse = UseSU->getInstr();
268 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
272 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx,
285 const MachineInstr *MI = SU->getInstr();
305 !DefSU->getInstr()->registerDefIsDead(*Alias))) {
311 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
365 const MachineInstr *MI = SU->getInstr();
389 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr());
405 MachineInstr *MI = SU->getInstr();
    [all...]
SlotIndexes.cpp 184 MachineInstr *SlotMI = ListI->getInstr();
222 if (itr->getInstr() != 0) {
223 dbgs() << *itr->getInstr();
MachineScheduler.cpp 653 MachineInstr *MI = SU->getInstr();
793 if (TII->getLdStBaseRegImmOfs(SU->getInstr(), BaseReg, Offset, TRI))
808 if (TII->shouldClusterLoads(SUa->getInstr(), SUb->getInstr(), ClusterLength)
839 if (!SU->getInstr()->mayLoad())
883 MachineInstr *Branch = DAG->ExitSU.getInstr();
889 if (!TII->shouldScheduleAdjacent(SU->getInstr(), Branch))
    [all...]
DFAPacketizer.cpp 170 MIToSUnit[SU->getInstr()] = SU;
AggressiveAntiDepBreaker.cpp 720 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
739 CriticalPathMI = CriticalPathSU->getInstr();
784 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : 0;
    [all...]
CriticalAntiDepBreaker.cpp 425 MISUnitMap[SU->getInstr()] = SU;
446 MachineInstr *CriticalPathMI = CriticalPathSU->getInstr();
551 CriticalPathMI = CriticalPathSU->getInstr();
PostRASchedulerList.cpp 755 BB->splice(RegionEnd, BB, SU->getInstr());
  /external/llvm/include/llvm/CodeGen/
SlotIndexes.h 46 MachineInstr* getInstr() const { return mi; }
396 return index.isValid() ? index.listEntry()->getInstr() : 0;
405 if (I->getInstr())
588 assert(miEntry->getInstr() == mi && "Instruction indexes broken.");
603 assert(miEntry->getInstr() == mi &&
ScheduleDAG.h 402 /// getInstr - Return the representative MachineInstr for this SUnit.
404 MachineInstr *getInstr() const {
583 if (SU->isInstr()) return &SU->getInstr()->getDesc();
ScheduleDAGInstrs.h 155 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
  /external/llvm/lib/Target/PowerPC/
PPCHazardRecognizers.cpp 140 MachineInstr *MI = SU->getInstr();
198 MachineInstr *MI = SU->getInstr();

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