| /external/webkit/Source/JavaScriptCore/assembler/ |
| ARMAssembler.cpp | 95 ARMWord imm1; local
132 imm1 = OP2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8);
135 imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
169 imm1 = OP2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8);
190 mov_r(reg, imm1);
193 mvn_r(reg, imm1);
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 300 uint64_t Imm1, uint64_t Imm2);
326 uint64_t Imm1, uint64_t Imm2);
337 uint64_t Imm1, uint64_t Imm2);
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGNode.h | 199 Node(NodeType op, ExceptionInfo exceptionInfo, OpInfo imm1, OpInfo imm2, NodeIndex child1 = NoNode, NodeIndex child2 = NoNode, NodeIndex child3 = NoNode)
207 , m_opInfo(imm1.m_value)
|
| DFGSpeculativeJIT.cpp | 368 int32_t imm1; local
369 if (isDoubleConstantWithInt32Value(node.child1, imm1)) {
374 speculationCheck(m_jit.branchAdd32(MacroAssembler::Overflow, reg, Imm32(imm1), result.registerID()));
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 136 uint64_t Imm1, uint64_t Imm2);
458 uint64_t Imm1, uint64_t Imm2) {
464 .addImm(Imm1).addImm(Imm2));
467 .addImm(Imm1).addImm(Imm2));
[all...] |
| Thumb2SizeReduction.cpp | 60 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
[all...] |
| ARMCodeEmitter.cpp | 771 // Encode imm16 as imm4:imm1, same as movw above.
[all...] |
| /external/llvm/lib/Target/X86/ |
| README-SSE.txt | 502 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/valgrind/main/VEX/priv/ |
| host_ppc_defs.c | [all...] |
| guest_arm_toIR.c | 2613 UInt imm1 = SLICE_UInt(i0,10,10); local
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.td | 399 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
400 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXIntrinsics.td | [all...] |
