| /external/webkit/Source/JavaScriptCore/assembler/ |
| ARMAssembler.cpp | 96 ARMWord imm2; local
133 imm2 = OP2_IMM | ((imm >> 8) & 0xff) | (((rol + 8) & 0xf) << 8);
155 imm2 = OP2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
184 imm2 = OP2_IMM | (imm >> 24) | ((rol & 0xf) << 8);
191 orr_r(reg, reg, imm2);
194 bic_r(reg, reg, imm2);
|
| /external/webkit/Source/JavaScriptCore/dfg/ |
| DFGSpeculativeJIT.cpp | 380 int32_t imm2; local
381 if (isDoubleConstantWithInt32Value(node.child2, imm2)) {
386 speculationCheck(m_jit.branchAdd32(MacroAssembler::Overflow, reg, Imm32(imm2), result.registerID()));
413 int32_t imm2; local
414 if (isDoubleConstantWithInt32Value(node.child2, imm2)) {
419 speculationCheck(m_jit.branchSub32(MacroAssembler::Overflow, reg, Imm32(imm2), result.registerID()));
|
| DFGNode.h | 199 Node(NodeType op, ExceptionInfo exceptionInfo, OpInfo imm1, OpInfo imm2, NodeIndex child1 = NoNode, NodeIndex child2 = NoNode, NodeIndex child3 = NoNode)
209 m_constantValue.opInfo2 = imm2.m_value;
|
| /external/llvm/include/llvm/CodeGen/ |
| FastISel.h | 300 uint64_t Imm1, uint64_t Imm2);
326 uint64_t Imm1, uint64_t Imm2);
337 uint64_t Imm1, uint64_t Imm2);
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FastISel.cpp | [all...] |
| /external/valgrind/main/none/tests/ppc32/ |
| test_dfp5.c | 234 typedef void (*test_func_t)(unsigned int imm, unsigned int imm2, dfp_val_t valB);
|
| /external/valgrind/main/none/tests/ppc64/ |
| test_dfp5.c | 234 typedef void (*test_func_t)(unsigned int imm, unsigned int imm2, dfp_val_t valB);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /dalvik/vm/compiler/codegen/arm/ |
| ArmLIR.h | 624 rd[11-8] imm2[7-6] [0] msb[4-0] */
626 rd[11-8] imm2[7-6] [0] msb[4-0] */
[all...] |
| Assemble.cpp | 2635 int imm2 = (insn >> 4) & 0x3; local
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMInstrThumb2.td | 249 // t2addrmode_so_reg := reg + (reg << imm2)
572 let Inst{7-6} = 0b00; // imm2
653 let Inst{7-6} = 0b00; // imm2
765 let Inst{7-6} = 0b00; // imm2
806 let Inst{7-6} = 0b00; // imm2
902 let Inst{7-6} = 0b00; // imm2
[all...] |
| ARMFastISel.cpp | 136 uint64_t Imm1, uint64_t Imm2);
458 uint64_t Imm1, uint64_t Imm2) {
464 .addImm(Imm1).addImm(Imm2));
467 .addImm(Imm1).addImm(Imm2));
[all...] |
| Thumb2SizeReduction.cpp | 60 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
[all...] |
| /external/valgrind/main/VEX/priv/ |
| host_ppc_defs.c | [all...] |
| /external/qemu/ |
| elf.h | [all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| Assemble.cpp | 2016 int imm2 = (insn >> 4) & 0x3; local
[all...] |
| /external/llvm/lib/Target/X86/ |
| README-SSE.txt | 502 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonInstrInfo.td | 399 class COMBINE_imm<Operand imm1, Operand imm2, PatLeaf pat1, PatLeaf pat2> :
400 ALU32_ii<(outs DoubleRegs:$dst), (ins imm1:$src1, imm2:$src2),
[all...] |
| /external/elfutils/libelf/ |
| elf.h | [all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXIntrinsics.td | [all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.4.3/sysroot/usr/include/ |
| elf.h | [all...] |
| /prebuilts/gcc/linux-x86/host/i686-linux-glibc2.7-4.6/sysroot/usr/include/ |
| elf.h | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.7-4.6/sysroot/usr/include/ |
| elf.h | [all...] |
