| /external/llvm/test/CodeGen/AArch64/ |
| movw-consts.ll | 12 ; CHECK: movz x0, #1
18 ; CHECK: movz x0, #65535
24 ; CHECK: movz x0, #1, lsl #16
30 ; CHECK: movz x0, #65535, lsl #16
36 ; CHECK: movz x0, #1, lsl #32
42 ; CHECK: movz x0, #65535, lsl #32
48 ; CHECK: movz x0, #1, lsl #48
85 ; CHECK: movz {{w[0-9]+}}, #1
92 ; CHECK: movz {{w[0-9]+}}, #65535
99 ; CHECK: movz {{w[0-9]+}}, #1, lsl #1
[all...] |
| i128-align.ll | 16 ; CHECK: movz x0, #48
28 ; CHECK: movz x0, #16
|
| large-frame.ll | 15 ; CHECK: movz [[SUBCONST:x[0-9]+]], #22576
20 ; CHECK: movz [[VAR1OFFSET:x[0-9]+]], #11544
28 ; CHECK: movz [[VAR2OFFSET:x[0-9]+]], #11528
41 ; CHECK: movz [[ADDCONST:x[0-9]+]], #22576
103 ; CHECK-NOT: movz {{x[0-7],}}
106 ; CHECK-NOT: movz {{x[0-7],}}
|
| directcond.ll | 6 ; CHECK: movz [[ONE:w[0-9]+]], #1
16 ; CHECK: movz [[ONE:w[0-9]+]], #1
26 ; CHECK: movz [[ONE:w[0-9]+]], #1
36 ; CHECK: movz [[ONE:w[0-9]+]], #1
|
| tls-execs.ll | 41 ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
56 ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
|
| cond-sel.ll | 12 ; CHECK: movz [[W52:w[0-9]+]], #52
13 ; CHECK: movz [[W42:w[0-9]+]], #42
35 ; CHECK: movz [[W52:w[0-9]+]], #52
36 ; CHECK: movz [[W42:w[0-9]+]], #42
45 ; CHECK: movz [[CONST15:x[0-9]+]], #15
46 ; CHECK: movz [[CONST9:x[0-9]+]], #9
|
| tls-dynamics.ll | 63 ; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
86 ; CHECK: movz [[DTP_OFFSET:x[0-9]+]], #:dtprel_g1:local_dynamic_var
|
| tst-br.ll | 39 ; CHECK: movz x0, #1
|
| /external/llvm/test/CodeGen/X86/ |
| sext-trunc.ll | 3 ; RUN: not grep movz %t
|
| 2008-09-29-VolatileBug.ll | 1 ; RUN: llc < %s -march=x86 | not grep movz
|
| vec_set-H.ll | 1 ; RUN: llc < %s -march=x86 -mattr=+sse2 | not grep movz
|
| /external/llvm/test/MC/AArch64/ |
| elf-reloc-movw.s | 4 movz x0, #:abs_g0:some_label
7 movz x3, #:abs_g1:some_label
10 movz x3, #:abs_g2:some_label
13 movz x7, #:abs_g3:some_label
16 movz x13, #:abs_g0_s:some_label
19 movz x19, #:abs_g1_s:some_label
22 movz x19, #:abs_g2_s:some_label
|
| tls-relocs.s | 9 movz x1, #:dtprel_g2:var
11 movz x3, #:dtprel_g2:var
13 // CHECK: movz x1, #:dtprel_g2:var // encoding: [0x01'A',A,0xc0'A',0x92'A']
17 // CHECK-NEXT: movz x3, #:dtprel_g2:var // encoding: [0x03'A',A,0xc0'A',0x92'A']
44 movz x5, #:dtprel_g1:var
46 movz w7, #:dtprel_g1:var
48 // CHECK: movz x5, #:dtprel_g1:var // encoding: [0x05'A',A,0xa0'A',0x92'A']
52 // CHECK-NEXT: movz w7, #:dtprel_g1:var // encoding: [0x07'A',A,0xa0'A',0x12'A']
98 movz x11, #:dtprel_g0:var
100 movz w13, #:dtprel_g0:va
[all...] |
| /external/llvm/test/CodeGen/Mips/ |
| cmov.ll | 44 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
54 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
67 ; (movz t, (setlt a, N + 1), f)
72 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
93 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
116 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
137 ; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
160 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
181 ; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
|
| zeroreg.ll | 16 ; CHECK: movz ${{[0-9]+}}, $zero
|
| /external/llvm/lib/Target/X86/ |
| X86InstrExtension.td | 67 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
71 "movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
75 "movz{bl|x}\t{$src, $dst|$dst, $src}",
78 "movz{bl|x}\t{$src, $dst|$dst, $src}",
81 "movz{wl|x}\t{$src, $dst|$dst, $src}",
84 "movz{wl|x}\t{$src, $dst|$dst, $src}",
94 "movz{bl|x}\t{$src, $dst|$dst, $src}",
99 "movz{bl|x}\t{$src, $dst|$dst, $src}",
130 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>,
133 "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>
[all...] |
| /frameworks/native/opengl/libagl/arch-mips/ |
| fixed_asm.S | 52 movz $v0,$zero,$t1
53 movz $v0,$zero,$t3 /* t3=0 then res=0 */
59 movz $v0,$t1,$t0 /* positive, maximum value */
|
| /external/llvm/lib/Target/Mips/ |
| MipsCondMov.td | 106 def MOVZ_I_I : CMov_I_I_FT<"movz", CPURegs, CPURegs, NoItinerary>,
110 def MOVZ_I_I64 : CMov_I_I_FT<"movz", CPURegs, CPU64Regs, NoItinerary>,
112 def MOVZ_I64_I : CMov_I_I_FT<"movz", CPU64Regs, CPURegs, NoItinerary>,
116 def MOVZ_I64_I64 : CMov_I_I_FT<"movz", CPU64Regs, CPU64Regs, NoItinerary>,
138 def MOVZ_I_S : CMov_I_F_FT<"movz.s", CPURegs, FGR32, IIFmove>,
140 def MOVZ_I64_S : CMov_I_F_FT<"movz.s", CPU64Regs, FGR32, IIFmove>,
153 def MOVZ_I_D32 : CMov_I_F_FT<"movz.d", CPURegs, AFGR64, IIFmove>,
160 def MOVZ_I_D64 : CMov_I_F_FT<"movz.d", CPURegs, FGR64, IIFmove>,
162 def MOVZ_I64_D64 : CMov_I_F_FT<"movz.d", CPU64Regs, FGR64, IIFmove>,
|
| /external/valgrind/main/none/tests/mips32/ |
| MoveIns.c | 569 printf("MOVZ.S\n");
570 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 0, 0, f0, f2, t3);
571 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 4, 1, f0, f2, t3);
572 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 8, 0xffff, f0, f2, t3);
573 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 12, -1, f0, f2, t3);
574 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 16, 5, f0, f2, t3);
575 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 20, 0, f0, f2, t3);
576 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 24, 0, f0, f2, t3);
577 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 24, 0, f0, f2, t3);
578 TESTINSNMOVEN1s("movz.s $f0, $f2, $t3", 28, 5, f0, f2, t3)
[all...] |
| MoveIns.stdout.exp | 305 MOVZ.S
306 movz.s $f0, $f2, $t3 :: fs rt 0x0
307 movz.s $f0, $f2, $t3 :: fs rt 0x0
308 movz.s $f0, $f2, $t3 :: fs rt 0x0
309 movz.s $f0, $f2, $t3 :: fs rt 0x0
310 movz.s $f0, $f2, $t3 :: fs rt 0x0
311 movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
312 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
313 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
314 movz.s $f0, $f2, $t3 :: fs rt 0x
[all...] |
| MoveIns.stdout.exp-BE | 305 MOVZ.S
306 movz.s $f0, $f2, $t3 :: fs rt 0x0
307 movz.s $f0, $f2, $t3 :: fs rt 0x0
308 movz.s $f0, $f2, $t3 :: fs rt 0x0
309 movz.s $f0, $f2, $t3 :: fs rt 0x0
310 movz.s $f0, $f2, $t3 :: fs rt 0x0
311 movz.s $f0, $f2, $t3 :: fs rt 0xc0e96d19
312 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
313 movz.s $f0, $f2, $t3 :: fs rt 0x4e6e6b28
314 movz.s $f0, $f2, $t3 :: fs rt 0x
[all...] |
| /external/openssl/crypto/aes/asm/ |
| aes-586.pl | 252 &movz ($s[2],&HB($s[0]));
257 &movz ($s[1],&HB($v1));
265 &movz ($v0,&HB($v1));
268 &movz ($v0,&HB($v1));
277 &movz ($v1,&HB($v0));
280 &movz ($v1,&HB($v0));
289 &movz ($v0,&HB($v1));
292 &movz ($v0,&HB($v1));
304 &movz ($v0,&LB($s0)); # 3, 2, 1, 0*
307 &movz ($v0,&HB($s1)); # 7, 6, 5*,
[all...] |
| /external/kernel-headers/original/asm-mips/ |
| asm.h | 166 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
176 #define MOVZ(rd, rs, rt) \
192 #define MOVZ(rd, rs, rt) \
204 #define MOVZ(rd, rs, rt) \
205 movz rd, rs, rt
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 383 COMPARE(movz(a0, a1, a2),
384 "00a6200a movz a0, a1, a2");
385 COMPARE(movz(s0, s1, s2),
386 "0232800a movz s0, s1, s2");
387 COMPARE(movz(t2, t3, t4),
388 "016c500a movz t2, t3, t4");
389 COMPARE(movz(v0, v1, a2),
390 "0066100a movz v0, v1, a2");
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64AsmBackend.cpp | 400 // R_AARCH64_MOVW_UABS_G0: Sets a MOVZ immediate field to bits FFFF of S+A
420 // R_AARCH64_MOVW_UABS_G1: Sets a MOVZ immediate field to bits FFFF0000 of
437 // R_AARCH64_MOVW_UABS_G2: Sets a MOVZ immediate field to bits FFFF 0000
448 // R_AARCH64_MOVW_UABS_G3: Sets a MOVZ immediate field to bits FFFF 0000
461 // should convert between MOVN and MOVZ to achieve our goals).
467 // Bit 30 converts the MOVN encoding into a MOVZ
488 // should convert between MOVN and MOVZ to achieve our goals).
494 // Bit 30 converts the MOVN encoding into a MOVZ
511 // we should convert between MOVN and MOVZ to achieve our goals).
517 // Bit 30 converts the MOVN encoding into a MOVZ
[all...] |
