| /external/llvm/test/CodeGen/PowerPC/ |
| vec_cmp.ll | 14 %sext = sext <2 x i1> %cmp to <2 x i8>
15 ret <2 x i8> %sext
23 %sext = sext <4 x i1> %cmp to <4 x i8>
24 ret <4 x i8> %sext
32 %sext = sext <8 x i1> %cmp to <8 x i8>
33 ret <8 x i8> %sext
43 %sext = sext <16 x i1> %cmp to <16 x i8
[all...] |
| 2007-01-04-ArgExtension.ll | 6 %tmp = sext i8 %c to i32 ; <i32> [#uses=1]
7 %tmp1 = sext i16 %s to i32 ; <i32> [#uses=1]
|
| /external/llvm/test/Transforms/InstCombine/ |
| 2007-08-02-InfiniteLoop.ll | 5 %W = sext i16 %tmp510 to i32 ; <i32> [#uses=1]
6 %X = sext i16 %tmp512 to i32 ; <i32> [#uses=1]
8 %Z = sext i32 %Y to i64 ; <i64> [#uses=1]
|
| bitcast-sext-vector.ll | 2 ; CHECK: sext
8 %sext = sext <4 x i1> %cmp to <4 x i8>
9 %val = bitcast <4 x i8> %sext to i32
|
| 2006-10-19-SignedToUnsignedCastAndConst-2.ll | 3 ; RUN: not grep sext.*i32
6 %Y = sext i8 %SB to i32 ; <i32> [#uses=1]
|
| add-shrink.ll | 2 ; RUN: opt < %s -instcombine -S | grep sext | count 1
4 ; Should only have one sext and the add should be i32 instead of i64.
9 %D = sext i32 %B to i64 ; <i64> [#uses=1]
10 %E = sext i32 %C to i64 ; <i64> [#uses=1]
|
| 2012-04-30-SRem.ll | 7 %sext = shl i32 %z, 24
8 %s = ashr exact i32 %sext, 24
|
| sext.ll | 11 %s = sext i32 %t to i64
20 %s = sext i32 %t to i64
29 %s = sext i32 %t to i64
38 %s = sext i32 %t to i64
47 %s = sext i32 %t to i64
56 %s = sext i32 %t to i64
65 %s = sext i32 %u to i64
75 %n = sext i16 %s to i32
88 %t2 = sext i16 %t to i32
109 %b = sext i8 %a to i32
[all...] |
| 2011-05-02-VectorBoolean.ll | 13 %sext = sext <2 x i1> %cmp to <2 x i16>
14 ret <2 x i16> %sext
|
| udiv-simplify-bug-1.ll | 7 ; sext instructions should be optimized to zext.
12 %z = sext i32 %r to i64
18 %z = sext i32 %r to i64
|
| udiv-simplify-bug-0.ll | 6 %z = sext i32 %r to i64
12 %z = sext i32 %r to i64
|
| /external/llvm/test/CodeGen/XCore/ |
| sext.ll | 4 %2 = sext i1 %1 to i32
8 ; CHECK: sext r0, 1
12 %2 = sext i2 %1 to i32
16 ; CHECK: sext r0, 2
20 %2 = sext i8 %1 to i32
24 ; CHECK: sext r0, 8
28 %2 = sext i16 %1 to i32
32 ; CHECK: sext r0, 16
|
| /external/llvm/test/Analysis/CostModel/X86/ |
| cast.ll | 11 ;CHECK: cost of 2 {{.*}} sext
12 %B = sext <4 x i1> undef to <4 x i32>
19 ;CHECK-NOT: cost of 2 {{.*}} sext
20 %E = sext <8 x i1> undef to <8 x i32>
38 ;CHECK: cost of 9 {{.*}} sext
39 %S = sext <8 x i1> %in to <8 x i32>
41 ;CHECK: cost of 1 {{.*}} sext
42 %A = sext <8 x i16> undef to <8 x i32>
45 ;CHECK: cost of 1 {{.*}} sext
46 %C = sext <4 x i32> undef to <4 x i64
[all...] |
| /external/llvm/test/CodeGen/X86/ |
| pmovsx-inreg.ll | 10 %sext = sext <2 x i8> %wide.load35 to <2 x i64>
12 store <2 x i64> %sext, <2 x i64>* %out, align 8
27 %sext = sext <4 x i8> %wide.load35 to <4 x i64>
29 store <4 x i64> %sext, <4 x i64>* %out, align 8
38 %sext = sext <4 x i8> %wide.load35 to <4 x i32>
40 store <4 x i32> %sext, <4 x i32>* %out, align 8
55 %sext = sext <8 x i8> %wide.load35 to <8 x i32
[all...] |
| pr3216.ll | 15 %bf.val.sext = ashr i8 %1, 5
16 %conv = sext i8 %bf.val.sext to i32
|
| vec_sext.ll | 6 %G = sext <4 x i16> %F to <4 x i32>
8 %Y = sext <4 x i16> %H to <4 x i32>
16 %G = sext <4 x i16> %F to <4 x i64>
18 %Y = sext <4 x i16> %H to <4 x i64>
26 %G = sext <4 x i32> %F to <4 x i64>
28 %Y = sext <4 x i32> %H to <4 x i64>
35 %G = sext <4 x i8> %F to <4 x i16>
37 %Y = sext <4 x i8> %H to <4 x i16>
44 %G = sext <4 x i8> %F to <4 x i32>
46 %Y = sext <4 x i8> %H to <4 x i32
[all...] |
| extmul128.ll | 4 %aa = sext i64 %a to i128
5 %bb = sext i64 %b to i128
|
| extmul64.ll | 4 %aa = sext i32 %a to i64
5 %bb = sext i32 %b to i64
|
| /external/llvm/test/CodeGen/Mips/ |
| vector-setcc.ll | 12 %sext = sext <4 x i1> %cmp to <4 x i32>
13 store <4 x i32> %sext, <4 x i32>* @g0, align 16
|
| madd-msub.ll | 6 %conv = sext i32 %a to i64
7 %conv2 = sext i32 %b to i64
9 %conv4 = sext i32 %c to i64
28 %conv = sext i32 %a to i64
29 %conv2 = sext i32 %b to i64
38 %conv = sext i32 %c to i64
39 %conv2 = sext i32 %a to i64
40 %conv4 = sext i32 %b to i64
60 %conv = sext i32 %a to i64
61 %conv3 = sext i32 %b to i6
[all...] |
| /external/llvm/test/CodeGen/R600/ |
| setcc.v4i32.ll | 9 %sext = sext <4 x i1> %result to <4 x i32>
10 store <4 x i32> %sext, <4 x i32> addrspace(1)* %out
|
| /external/llvm/test/Transforms/IndVarSimplify/ |
| preserve-signed-wrap.ll | 4 ; sext for the addressing, however it shouldn't eliminate the sext
17 ; CHECK: sext i8
18 ; CHECK-NOT: sext
22 %1 = sext i8 %p.01 to i32 ; <i32> [#uses=1]
23 %2 = sext i32 %i.02 to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/ARM/ |
| smml.ll | 6 %conv1 = sext i32 %b to i64
7 %conv2 = sext i32 %c to i64
|
| fast-isel-crash2.ll | 7 %r = sext i4 %t to i32
|
| /external/llvm/test/CodeGen/Generic/ |
| 2005-12-12-ExpandSextInreg.ll | 5 %C = sext i8 %B to i64 ; <i64> [#uses=1]
|
