| /external/llvm/test/CodeGen/PowerPC/ |
| 2004-11-30-shr-var-crash.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=1]
5 %shift.upgrd.1 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/CodeGen/X86/ |
| shift-bmi2.ll | 4 define i32 @shl32(i32 %x, i32 %shamt) nounwind uwtable readnone {
6 %shl = shl i32 %x, %shamt
28 define i32 @shl32p(i32* %p, i32 %shamt) nounwind uwtable readnone {
31 %shl = shl i32 %x, %shamt
54 define i64 @shl64(i64 %x, i64 %shamt) nounwind uwtable readnone {
56 %shl = shl i64 %x, %shamt
72 define i64 @shl64p(i64* %p, i64 %shamt) nounwind uwtable readnone {
75 %shl = shl i64 %x, %shamt
92 define i32 @lshr32(i32 %x, i32 %shamt) nounwind uwtable readnone {
94 %shl = lshr i32 %x, %shamt
[all...] |
| shift-and.ll | 12 %shamt = and i32 %t, 31
13 %res = shl i32 %val, %shamt
25 %shamt = and i32 %t, 63
26 %res = shl i32 %val, %shamt
40 %shamt = and i16 %t, 31
42 %tmp1 = ashr i16 %tmp, %shamt
51 %shamt = and i64 %t, 63
52 %res = lshr i64 %val, %shamt
60 %shamt = and i64 %t, 191
61 %res = lshr i64 %val, %shamt
[all...] |
| vshift-5.ll | 12 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
13 %shl = shl <4 x i32> %val, %shamt
26 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
27 %shr = ashr <4 x i32> %val, %shamt
39 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
40 %shl = shl <4 x i32> %val, %shamt
52 %shamt = shufflevector <4 x i32> %tmp0, <4 x i32> undef, <4 x i32> zeroinitializer
53 %shr = ashr <4 x i32> %val, %shamt
|
| vshift-4.ll | 10 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
11 %shl = shl <2 x i64> %val, %shamt
21 %shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
22 %shl = shl <2 x i64> %val, %shamt
31 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
32 %shl = shl <4 x i32> %val, %shamt
41 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
42 %shl = shl <4 x i32> %val, %shamt
51 %shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
52 %shl = shl <4 x i32> %val, %shamt
[all...] |
| /external/llvm/test/ExecutionEngine/MCJIT/ |
| test-shift.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/test/ExecutionEngine/ |
| test-shift.ll | 4 %shamt = add i8 0, 1 ; <i8> [#uses=8]
5 %shift.upgrd.1 = zext i8 %shamt to i32 ; <i32> [#uses=1]
8 %shift.upgrd.2 = zext i8 %shamt to i32 ; <i32> [#uses=1]
13 %shift.upgrd.5 = zext i8 %shamt to i32 ; <i32> [#uses=1]
16 %shift.upgrd.6 = zext i8 %shamt to i32 ; <i32> [#uses=1]
20 %shift.upgrd.7 = zext i8 %shamt to i64 ; <i64> [#uses=1]
23 %shift.upgrd.8 = zext i8 %shamt to i64 ; <i64> [#uses=1]
26 %shift.upgrd.9 = zext i8 %shamt to i64 ; <i64> [#uses=1]
29 %shift.upgrd.10 = zext i8 %shamt to i64 ; <i64> [#uses=1]
|
| /external/llvm/lib/Target/Mips/ |
| MipsAnalyzeImmediate.cpp | 43 unsigned Shamt = CountTrailingZeros_64(Imm);
44 GetInstSeqLs(Imm >> Shamt, RemSize - Shamt, SeqLs);
45 AddInstr(SeqLs, Inst(SLL, Shamt));
|
| Mips64InstrInfo.td | 31 // shamt must fit in 6 bits.
103 def DSLL : shift_rotate_imm<"dsll", shamt, CPU64RegsOpnd, shl, immZExt6>,
105 def DSRL : shift_rotate_imm<"dsrl", shamt, CPU64RegsOpnd, srl, immZExt6>,
107 def DSRA : shift_rotate_imm<"dsra", shamt, CPU64RegsOpnd, sra, immZExt6>,
112 def DSLL32 : shift_rotate_imm<"dsll32", shamt, CPU64RegsOpnd>, SRA_FM<0x3c, 0>;
113 def DSRL32 : shift_rotate_imm<"dsrl32", shamt, CPU64RegsOpnd>, SRA_FM<0x3e, 0>;
114 def DSRA32 : shift_rotate_imm<"dsra32", shamt, CPU64RegsOpnd>, SRA_FM<0x3f, 0>;
119 def DROTR : shift_rotate_imm<"drotr", shamt, CPU64RegsOpnd, rotr, immZExt6>,
221 let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
|
| MipsInstrFormats.td | 19 // shamt - only used on shift instructions, contains the shift amount.
106 // Format R instruction class in Mips : <|opcode|rs|rt|rd|shamt|funct|>
116 bits<5> shamt;
125 let Inst{10-6} = shamt;
226 bits<5> shamt;
235 let Inst{10-6} = shamt;
|
| MipsInstrInfo.td | 241 def shamt : Operand<i32>;
334 // shamt field must fit in 5 bits.
402 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
403 !strconcat(opstr, "\t$rd, $rt, $shamt"),
404 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
828 def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
830 def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
832 def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
840 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>,
[all...] |
| MipsISelLowering.cpp | 806 unsigned Shamt = CN->getZExtValue();
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 581 unsigned ShAmt = SA->getZExtValue();
585 if (ShAmt >= BitWidth)
588 // If this is ((X >>u C1) << ShAmt), see if we can simplify this into a
593 if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
596 int Diff = ShAmt-C1;
610 if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt),
620 if (ShAmt < InnerBits && NewMask.lshr(InnerBits) == 0 &&
623 if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits()))
627 TLO.DAG.getConstant(ShAmt, ShTy))
[all...] |
| LegalizeVectorOps.cpp | 450 SDValue Lo, Hi, ShAmt;
453 ShAmt = DAG.getConstant(BitOffset, TLI.getShiftAmountTy(WideVT));
454 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt);
463 ShAmt = DAG.getConstant(SrcEltBits - Offset,
465 Hi = DAG.getNode(ISD::SHL, dl, WideVT, LoadVals[WideIdx], ShAmt);
482 ShAmt = DAG.getConstant(WideBits - SrcEltBits,
484 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt);
485 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt);
|
| /system/core/libpixelflinger/codeflinger/ |
| mips_disassem.c | 221 reg_name[i.RType.rt], i.RType.shamt);
224 if (i.RType.func == OP_SRLV && (i.RType.shamt & 1) == 1) {
246 i.RType.shamt);
327 i.RType.shamt);
333 i.RType.shamt);
334 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_WSBH)
338 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEB)
342 else if (i.RType.func == OP_BSHFL && i.RType.shamt == OP_SEH)
|
| mips_opcode.h | 65 unsigned shamt: 5; member in struct:__anon43974::__anon43977
100 unsigned shamt: 5; member in struct:__anon43974::__anon43981
270 * Values for the 'shamt' field when OP_SPECIAL3 && func OP_BSHFL.
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineShifts.cpp | 370 Constant *ShAmt = ConstantExpr::getZExt(Op1, TrOp->getType());
372 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName());
687 unsigned ShAmt = Op1C->getZExtValue();
692 APInt::getHighBitsSet(Op1C->getBitWidth(), ShAmt))) {
699 ComputeNumSignBits(I.getOperand(0)) > ShAmt) {
726 unsigned ShAmt = Op1C->getZExtValue();
736 isPowerOf2_32(BitWidth) && Log2_32(BitWidth) == ShAmt) {
746 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
766 unsigned ShAmt = Op1C->getZExtValue();
792 MaskedValueIsZero(Op0,APInt::getLowBitsSet(Op1C->getBitWidth(),ShAmt))){
[all...] |
| InstCombineCompares.cpp | [all...] |
| InstCombineCasts.cpp | [all...] |
| /external/clang/lib/Lex/ |
| PPExpressions.cpp | 595 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
597 Overflow = ShAmt >= LHS.Val.getBitWidth();
599 ShAmt = LHS.Val.getBitWidth()-1;
600 Res = LHS.Val << ShAmt;
602 Res = llvm::APSInt(LHS.Val.sshl_ov(ShAmt, Overflow), false);
608 unsigned ShAmt = static_cast<unsigned>(RHS.Val.getLimitedValue());
609 if (ShAmt >= LHS.getBitWidth())
610 Overflow = true, ShAmt = LHS.getBitWidth()-1;
611 Res = LHS.Val >> ShAmt;
|
| /external/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 95 ARM_AM::ShiftOpc ShOpcVal, unsigned ShAmt);
464 unsigned ShAmt) {
471 (ShAmt == 2 || (Subtarget->isSwift() && ShAmt == 1));
590 unsigned ShAmt = Log2_32(RHSC);
592 Opc = CurDAG->getTargetConstant(ARM_AM::getAM2Opc(AddSub, ShAmt,
618 unsigned ShAmt = 0;
628 ShAmt = Sh->getZExtValue();
629 if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
632 ShAmt = 0
[all...] |
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MIPSAssembler.h | 377 void sll(RegisterID rd, RegisterID rt, int shamt)
380 | ((shamt & 0x1f) << OP_SH_SHAMT));
389 void sra(RegisterID rd, RegisterID rt, int shamt)
392 | ((shamt & 0x1f) << OP_SH_SHAMT));
401 void srl(RegisterID rd, RegisterID rt, int shamt)
404 | ((shamt & 0x1f) << OP_SH_SHAMT));
|
| /external/llvm/lib/Transforms/Scalar/ |
| ScalarReplAggregates.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrShiftRotate.td | [all...] |
| /external/llvm/lib/IR/ |
| ConstantFold.cpp | 255 unsigned ShAmt = Amt->getZExtValue();
257 if ((ShAmt & 7) != 0)
259 ShAmt >>= 3;
262 if (ByteStart >= CSize-ShAmt)
266 if (ByteStart+ByteSize+ShAmt <= CSize)
267 return ExtractConstantBytes(CE->getOperand(0), ByteStart+ShAmt, ByteSize);
277 unsigned ShAmt = Amt->getZExtValue();
279 if ((ShAmt & 7) != 0)
281 ShAmt >>= 3;
284 if (ByteStart+ByteSize <= ShAmt)
[all...] |
