| /external/llvm/test/CodeGen/Mips/ |
| srl2.ll | 13 ; 16: srlv ${{[0-9]+}}, ${{[0-9]+}}
|
| atomic.ll | 98 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
129 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
161 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
191 ; CHECK: srlv $[[R16:[0-9]+]], $[[R15]], $[[R4]]
226 ; CHECK: srlv $[[R16:[0-9]+]], $[[R13]], $[[R4]]
|
| /external/valgrind/main/none/tests/mips32/ |
| MIPS32int.c | [all...] |
| MIPS32int.stdout.exp | [all...] |
| MIPS32int.stdout.exp-BE | [all...] |
| MIPS32int.stdout.exp-mips32 | [all...] |
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | 252 COMPARE(srlv(a0, a1, a2),
253 "00c52006 srlv a0, a1, a2");
254 COMPARE(srlv(s0, s1, s2),
255 "02518006 srlv s0, s1, s2");
256 COMPARE(srlv(t2, t3, t4),
257 "018b5006 srlv t2, t3, t4");
258 COMPARE(srlv(v0, v1, fp),
259 "03c31006 srlv v0, v1, fp");
|
| /external/kernel-headers/original/asm-mips/ |
| asm.h | 265 #define INT_SRLV srlv
302 #define LONG_SRLV srlv
351 #define PTR_SRLV srlv
|
| /bionic/libc/kernel/arch-mips/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/8/platforms/android-14/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /prebuilts/ndk/8/platforms/android-9/arch-mips/usr/include/asm/ |
| asm.h | 120 #define INT_SRLV srlv
160 #define LONG_SRLV srlv
212 #define PTR_SRLV srlv
|
| /external/llvm/test/MC/Mips/ |
| mips-alu-instructions.s | 29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
56 srlv $2, $3, $5
|
| mips64-alu-instructions.s | 29 # CHECK: srlv $2, $3, $5 # encoding: [0x06,0x10,0xa3,0x00]
56 srlv $2, $3, $5
|
| /external/v8/src/mips/ |
| constants-mips.cc | 247 case SRLV:
|
| disasm-mips.cc | 652 case SRLV:
654 Format(instr, "srlv 'rd, 'rt, 'rs");
|
| assembler-mips.cc | 1303 void Assembler::srlv(Register rd, Register rt, Register rs) { function in class:v8::Assembler
[all...] |
| constants-mips.h | 308 SRLV = ((0 << 3) + 6),
|
| /external/llvm/test/MC/Disassembler/Mips/ |
| mips32.txt | 366 # CHECK: srlv $2, $3, $5
|
| mips32_le.txt | 366 # CHECK: srlv $2, $3, $5
|
| mips32r2.txt | 387 # CHECK: srlv $2, $3, $5
|
| mips32r2_le.txt | 387 # CHECK: srlv $2, $3, $5
|
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | [all...] |
| /dalvik/vm/compiler/codegen/mips/ |
| MipsLIR.h | 457 kMipsSrlv, /* srlv d,t,s [000000] s[25..21] t[20..16] d[15..11] [00000000110] */
|
| /external/webkit/Source/JavaScriptCore/assembler/ |
| MIPSAssembler.h | 407 void srlv(RegisterID rd, RegisterID rt, RegisterID rs) function in class:JSC::MIPSAssembler
|
