HomeSort by relevance Sort by last modified time
    Searched full:ssse3 (Results 1 - 25 of 168) sorted by null

1 2 3 4 5 6 7

  /external/valgrind/main/none/tests/amd64/
ssse3_misaligned.vgtest 2 prereq: ../../../tests/x86_amd64_features amd64-ssse3
insn_ssse3.vgtest 2 prereq: ../../../tests/x86_amd64_features amd64-ssse3
  /external/valgrind/main/none/tests/x86/
ssse3_misaligned.vgtest 2 prereq: test -x ssse3_misaligned && ../../../tests/x86_amd64_features x86-ssse3
insn_ssse3.vgtest 2 prereq: test -x insn_ssse3 && ../../../tests/x86_amd64_features x86-ssse3
  /external/llvm/test/CodeGen/X86/
avx-sext.ll 2 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSSE3
25 ; SSSE3: load_sext_test1
26 ; SSSE3: movq
27 ; SSSE3: punpcklwd %xmm{{.*}}, %xmm{{.*}}
28 ; SSSE3: psrad $16
29 ; SSSE3: ret
46 ; SSSE3: load_sext_test2
47 ; SSSE3: movd
48 ; SSSE3: pshufb
49 ; SSSE3: psrad $2
    [all...]
phaddsub.ll 1 ; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
2 ; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
4 ; SSSE3: phaddw1:
5 ; SSSE3-NOT: vphaddw
6 ; SSSE3: phaddw
16 ; SSSE3: phaddw2:
17 ; SSSE3-NOT: vphaddw
18 ; SSSE3: phaddw
28 ; SSSE3: phaddd1
    [all...]
palignr-2.ll 1 ; RUN: llc < %s -march=x86 -mattr=+ssse3 | FileCheck %s
12 %0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
17 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
25 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) nounwind readnone
subtarget-feature-change.ll 61 attributes #0 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,-sse,-avx,-sse41,-ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,-sse2,-sse3" }
62 attributes #1 = { nounwind optsize ssp uwtable "target-cpu"="core2" "target-features"="-sse4a,-avx2,-xop,-fma4,-bmi2,-3dnow,-3dnowa,-pclmul,+sse,-avx,-sse41,+ssse3,+mmx,-rtm,-sse42,-lzcnt,-f16c,-popcnt,-bmi,-aes,-fma,-rdrand,+sse2,+sse3" }
  /external/clang/test/Sema/
x86-builtin-palignr.c 1 // RUN: %clang_cc1 -ffreestanding -fsyntax-only -target-feature +ssse3 -target-feature +mmx -verify -triple x86_64-pc-linux-gnu %s
2 // RUN: %clang_cc1 -ffreestanding -fsyntax-only -target-feature +ssse3 -target-feature +mmx -verify -triple i686-apple-darwin10 %s
  /external/libyuv/
README.google 9 Specifically libyuv is optimized for SSE2/SSSE3 and Neon and has demonstrated
  /external/clang/lib/Headers/
module.map 52 explicit module ssse3 {
53 requires ssse3
60 export ssse3
  /external/llvm/test/Bitcode/
ssse3_palignr.ll 8 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 15) ; <<2 x i64>> [#uses=1]
17 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 7) ; <<1 x i64>> [#uses=1]
23 declare <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64>, <1 x i64>, i8) nounwind readnone
29 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 16) ; <<1 x i64>> [#uses=1]
39 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 9) ; <<1 x i64>> [#uses=1]
49 %2 = tail call <1 x i64> @llvm.x86.ssse3.palign.r(<1 x i64> %1, <1 x i64> %0, i8 8) ; <<1 x i64>> [#uses=1]
59 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 32) ; <<2 x i64>> [#uses=1]
64 declare <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64>, <2 x i64>, i8) nounwind readnone
70 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 17) ; <<2 x i64>> [#uses=1]
79 %2 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %1, <2 x i64> %0, i8 16) ; <<2 x i64>> [#uses=1
    [all...]
  /bionic/libc/arch-x86/string/
bcopy_wrapper.S 39 # include "ssse3-memcpy5.S"
memcmp_wrapper.S 34 # include "ssse3-memcmp3-new.S"
memcpy_wrapper.S 37 # include "ssse3-memcpy5.S"
memmove_wrapper.S 37 # include "ssse3-memcpy5.S"
strcmp_wrapper.S 34 # include "ssse3-strcmp-latest.S"
strncmp_wrapper.S 35 # include "ssse3-strcmp-latest.S"
  /external/clang/test/CodeGen/
palignr.c 2 // RUN: %clang_cc1 %s -triple=i686-apple-darwin -target-feature +ssse3 -O1 -S -o - | FileCheck %s
  /external/libvpx/libvpx/test/
test_libvpx.cc 39 append_gtest_filter(":-SSSE3/*");
  /external/libvpx/libvpx/third_party/libyuv/include/libyuv/
cpu_id.h 39 // ie MaskCpuFlags(~kCpuHasSSSE3) to disable SSSE3.
  /external/skia/gyp/
opts.gyp 102 # create another target specifically for SSSE3 code as we would not want
104 # gcc to generate SSSE3 code.
121 # TODO(epoger): the following will enable SSSE3 on Macs, but it will
139 # is very similar to the SSSE3 one.
  /external/flac/libFLAC/
cpu.c 172 info->data.ia32.ssse3 = false;
186 info->data.ia32.ssse3 = (flags_ecx & FLAC__CPUINFO_IA32_CPUID_SSSE3)? true : false;
207 fprintf(stderr, " SSSE3 ...... %c\n", info->data.ia32.ssse3 ? 'Y' : 'n');
219 info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
229 info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
235 info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
240 info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
243 info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false;
282 info->data.ia32.fxsr = info->data.ia32.sse = info->data.ia32.sse2 = info->data.ia32.sse3 = info->data.ia32.ssse3 = false
    [all...]
  /external/libvpx/libvpx/vp8/common/
rtcd_defs.sh 143 specialize vp8_build_intra_predictors_mby_s sse2 ssse3
147 specialize vp8_build_intra_predictors_mbuv_s sse2 ssse3
195 specialize vp8_sixtap_predict16x16 mmx sse2 ssse3 media neon dspr2
200 specialize vp8_sixtap_predict8x8 mmx sse2 ssse3 media neon dspr2
205 specialize vp8_sixtap_predict8x4 mmx sse2 ssse3 media neon dspr2
210 specialize vp8_sixtap_predict4x4 mmx ssse3 media neon dspr2
215 specialize vp8_bilinear_predict16x16 mmx sse2 ssse3 media neon
219 specialize vp8_bilinear_predict8x8 mmx sse2 ssse3 media neon
272 specialize vp8_sub_pixel_variance16x8 mmx sse2 ssse3
276 specialize vp8_sub_pixel_variance16x16 mmx sse2 ssse3 media neo
    [all...]
  /external/libyuv/files/include/libyuv/
cpu_id.h 55 // ie MaskCpuFlags(~kCpuHasSSSE3) to disable SSSE3.

Completed in 1901 milliseconds

1 2 3 4 5 6 7