| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_TransformResidual4x4_s.S | 20 VSUB.I16 d6,d0,d2
23 VSUB.I16 d7,d7,d3
27 VSUB.I16 d2,d6,d7
28 VSUB.I16 d3,d5,d8
33 VSUB.I16 d6,d0,d2
36 VSUB.I16 d7,d7,d3
40 VSUB.I16 d2,d6,d7
41 VSUB.I16 d3,d5,d8
|
| omxVCM4P10_TransformDequantLumaDCFromPair_s.S | 25 VSUB.I16 d6,d0,d1
27 VSUB.I16 d7,d2,d3
30 VSUB.I16 d1,d4,d5
31 VSUB.I16 d2,d6,d7
39 VSUB.I16 d6,d0,d1
40 VSUB.I16 d7,d2,d3
42 VSUB.I16 d1,d4,d5
43 VSUB.I16 d2,d6,d7
|
| omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.S | 63 VSUB.I16 d6,d0,d2
66 VSUB.I16 d7,d7,d3
70 VSUB.I16 d2,d6,d7
71 VSUB.I16 d3,d5,d8
76 VSUB.I16 d6,d0,d2
79 VSUB.I16 d7,d7,d3
83 VSUB.I16 d2,d6,d7
84 VSUB.I16 d3,d5,d8
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.S | 40 VSUB.I16 d10,d10,d8
52 VSUB.I16 d12,d12,d8
64 VSUB.I16 d14,d14,d8
76 VSUB.I16 d16,d16,d8
88 VSUB.I16 d18,d18,d8
100 VSUB.I16 d20,d20,d8
112 VSUB.I16 d22,d22,d8
123 VSUB.I16 d24,d24,d8
131 VSUB.I16 d26,d26,d8
138 VSUB.I32 q5,q5,q
[all...] |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.S | 35 VSUB.I16 d22,d22,d8
47 VSUB.I16 d24,d24,d8
59 VSUB.I16 d26,d26,d8
|
| /external/llvm/test/CodeGen/ARM/ |
| fsubs.ll | 11 ; VFP2: vsub.f32 s
12 ; NFP1: vsub.f32 d
13 ; NFP0: vsub.f32 s
|
| fmscs.ll | 15 ; A8: vsub.f32
31 ; A8: vsub.f64
|
| fnmacs.ll | 15 ; A8: vsub.f32
31 ; A8: vsub.f64
|
| fnmscs.ll | 16 ; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
33 ; A8: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
50 ; A8: vsub.f64 d
67 ; A8: vsub.f64 d
|
| unsafe-fsub.ll | 11 ; SAFE: vsub.f32
|
| /external/llvm/test/MC/ARM/ |
| neon-sub-encoding.s | 3 vsub.i8 d16, d17, d16
4 vsub.i16 d16, d17, d16
5 vsub.i32 d16, d17, d16
6 vsub.i64 d16, d17, d16
7 vsub.f32 d16, d16, d17
8 vsub.i8 q8, q8, q9
9 vsub.i16 q8, q8, q9
10 vsub.i32 q8, q8, q9
11 vsub.i64 q8, q8, q9
12 vsub.f32 q8, q8, q
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_TransformResidual4x4_s.s | 121 VSUB de1,dIn0,dIn2 ;// e1 = d0 - d2
124 VSUB de2,dIn1RS,dIn3 ;// e2 = (d1>>1) - d3
128 VSUB df2,de1,de2 ;// f2 = e1 - e2
129 VSUB df3,de0,de3 ;// f3 = e0 - e3
148 VSUB dg1,df0,df2 ;// e1 = d0 - d2
151 VSUB dg2,df1RS,df3 ;// e2 = (d1>>1) - d3
155 VSUB dh2,dg1,dg2 ;// f2 = e1 - e2
156 VSUB dh3,dg0,dg3 ;// f3 = e0 - e3
|
| omxVCM4P10_TransformDequantLumaDCFromPair_s.s | 140 VSUB dRowDiff1,dIn0,dIn1
142 VSUB dRowDiff2,dIn2,dIn3
145 VSUB dRowOp1,dRowSum1,dRowSum2
146 VSUB dRowOp2,dRowDiff1,dRowDiff2
164 VSUB dColDiff1,dRowOp0,dRowOp1
165 VSUB dColDiff2,dRowOp2,dRowOp3
167 VSUB dColOp1,dColSum1,dColSum2
168 VSUB dColOp2,dColDiff1,dColDiff2
|
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 126 VSUB dRes0, dRes0, dTmp0 ;// TeRi
143 VSUB dRes1, dRes1, dTmp0
160 VSUB dRes2, dRes2, dTmp0
177 VSUB dRes3, dRes3, dTmp0
194 VSUB dRes4, dRes4, dTmp0
211 VSUB dRes5, dRes5, dTmp0
228 VSUB dRes6, dRes6, dTmp0
244 VSUB dRes7, dRes7, dTmp0
258 VSUB dRes8, dRes8, dTmp0
270 VSUB qAcc01, qAcc01, qTmp
[all...] |
| omxVCM4P10_DequantTransformResidualFromPairAndAdd_s.s | 295 VSUB de1,dIn0,dIn2 ;// e1 = d0 - d2
298 VSUB de2,dIn1RS,dIn3 ;// e2 = (d1>>1) - d3
302 VSUB df2,de1,de2 ;// f2 = e1 - e2
303 VSUB df3,de0,de3 ;// f3 = e0 - e3
322 VSUB dg1,df0,df2 ;// e1 = d0 - d2
325 VSUB dg2,df1RS,df3 ;// e2 = (d1>>1) - d3
329 VSUB dh2,dg1,dg2 ;// f2 = e1 - e2
330 VSUB dh3,dg0,dg3 ;// f3 = e0 - e3
|
| /external/libvpx/libvpx/vp8/encoder/arm/neon/ |
| vp8_shortwalsh4x4_neon.asm | 42 vsub.s16 d6, d1, d3 ; ip[1] - ip[3]
43 vsub.s16 d7, d0, d2 ; ip[0] - ip[2]
53 vsub.s16 d3, d4, d5 ; op[3] = a1 - d1
55 vsub.s16 d2, d7, d6 ; op[2] = b1 - c1
56 vsub.s16 d0, d0, d16 ; op[0] = a1 + d1 + (a1 != 0)
72 vsub.s32 q2, q11, q10 ; c2 = b1 - c1
73 vsub.s32 q3, q8, q9 ; d2 = a1 - d1
81 vsub.s32 q0, q0, q8 ; a2 += a2 < 0
82 vsub.s32 q1, q1, q9 ; b2 += b2 < 0
83 vsub.s32 q2, q2, q10 ; c2 += c2 <
[all...] |
| shortfdct_neon.asm | 52 vsub.s16 d6, d1, d2 ; c1 = ip[1] - ip[2]
53 vsub.s16 d7, d0, d3 ; d1 = ip[0] - ip[3]
59 vsub.s16 d2, d4, d5 ; op[2] = a1 - b1
82 vsub.s16 d6, d1, d2 ; c1 = ip[4] - ip[8]
84 vsub.s16 d7, d0, d3 ; d1 = ip[0] - ip[12]
87 vsub.s16 d2, d4, d5 ; op[8] = a1 - b1 + 7
102 vsub.s16 d1, d1, d4 ; op[4] += (d1!=0)
132 vsub.s16 q13, q1, q2 ; c1 = ip[1] - ip[2]
133 vsub.s16 q14, q0, q3 ; d1 = ip[0] - ip[3]
141 vsub.s16 q2, q11, q12 ; [A2 | B2] = a1 - b
[all...] |
| fastquantizeb_neon.asm | 79 vsub.s16 q4, q2 ; x1=(y^sz)-sz = (y^sz)-(-1) (2's complement)
80 vsub.s16 q5, q3
93 vsub.s16 q10, q12 ; x2=(y^sz)-sz = (y^sz)-(-1) (2's complement)
94 vsub.s16 q11, q13
208 vsub.s16 q12, q2 ; x1=(y^sz)-sz = (y^sz)-(-1) (2's complement)
209 vsub.s16 q13, q3
|
| /frameworks/av/media/libstagefright/codecs/aacenc/src/asm/ARMV7/ |
| R4R8First_v7.s | 45 VSUB.S32 d5, d0, d1 @ r1 = buf[0] - buf[2]@i1 = buf[1] - buf[3]@
46 VSUB.S32 d7, d2, d3 @ r2 = buf[4] - buf[6]@i2 = buf[5] - buf[7]@
51 VSUB.S32 Q1, Q2, Q3 @ r5 = (r0 - r2)@i5 = (i0 - i2)@r6 = (r1 - i3)@i7 = (i1 - r3)@
56 VSUB.S32 d7, d10, d11 @ r1 = buf[12] - buf[14]@i1 = buf[13] - buf[15]@
59 VSUB.S32 d5, d8, d9 @ r3 = buf[ 8] - buf[10]@i3 = buf[ 9] - buf[11]@
64 VSUB.S32 Q5, Q2, Q3 @ t2 = (r0 - r2) >> 1@t3 = (i0 - i2) >> 1@r0 = r1 - i3@i2 = i1 - r3@
79 VSUB.S32 d16, d0, d8
81 VSUB.S32 d18, d2, d10
83 VSUB.S32 d4, d11, d9
93 VSUB.S32 d15, d3, d
[all...] |
| Radix4FFT_v7.s | 70 VSUB.S32 Q3, Q12, Q13 @ MULHIGH(cosx, t1) - MULHIGH(sinx, t0)
76 VSUB.S32 Q0, Q10, Q2 @ r0 = t0 - r2@
77 VSUB.S32 Q1, Q11, Q3 @ r1 = t1 - r3@
91 VSUB.S32 Q9, Q12, Q13 @ MULHIGH(cosx, t1) - MULHIGH(sinx, t0)
102 VSUB.S32 Q7, Q12, Q13 @ MULHIGH(cosx, t1) - MULHIGH(sinx, t0)
105 VSUB.S32 Q5, Q7, Q9 @ r5 = r7 - t1@
106 VSUB.S32 Q6, Q8, Q6 @ r6 = t0 - r6@
113 VSUB.S32 Q10, Q2, Q4 @ xptr[0] = r2 - r4@
115 VSUB.S32 Q11, Q3, Q7 @ xptr[1] = r3 - r7@
118 VSUB.S32 Q8, Q0, Q5 @ xptr[0] = r0 - r5
[all...] |
| /external/libvpx/libvpx/vp8/common/arm/neon/ |
| iwalsh_neon.asm | 27 vsub.s16 d5, d0, d3 ;d = [0] - [12]
28 vsub.s16 d7, d1, d2 ;c = [4] - [8]
31 vsub.s16 q1, q2, q3 ; a-b d-c
47 vsub.s16 d5, d0, d3 ;d = [0] - [3]
48 vsub.s16 d7, d1, d2 ;c = [1] - [2]
53 vsub.s16 q1, q2, q3 ; a-b d-c
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| invalid-IT-CC15.txt | 16 # vsub.f64 d17, d17, d16
|
| /external/webp/src/dsp/ |
| enc_neon.c | 165 "vsub.s32 q2, q2, q3 \n" // tmp[8] = a0 - a1
167 "vsub.s32 q3, q5, q4 \n" // tmp[12] = a3 - a2
181 "vsub.s32 q8, q1, q2 \n" // a2 = tmp[1] - tmp[2]
182 "vsub.s32 q9, q0, q3 \n" // a3 = dc - tmp[3]
188 "vsub.s32 q2, q6, q7 \n"
190 "vsub.s32 q3, q9, q8 \n"
278 "vsub.s16 d6, d1, d2 \n" // a2 = d1 - d2
279 "vsub.s16 d7, d0, d3 \n" // a3 = d0 - d3
283 "vsub.s16 d2, d4, d5 \n" // a0 - a1
307 "vsub.s16 d6, d1, d2 \n" // c1 = ip[4] - ip[8
[all...] |
| /external/compiler-rt/lib/arm/ |
| subdf3vfp.S | 23 vsub.f64 d6, d6, d7
|
| subsf3vfp.S | 24 vsub.f32 s14, s14, s15
|
