Cross Reference: /dalvik/vm/compiler/codegen/x86/LowerAlu.cpp

Lines Matching full:set_virtual_reg
37     set_virtual_reg(vA, OpndSize_32, 1, false);
49     set_virtual_reg(vA, OpndSize_32, 1, false);
63     set_virtual_reg(vA, OpndSize_64, 2, false);
76     set_virtual_reg(vA, OpndSize_64, 1, false);
89     set_virtual_reg(vA, OpndSize_32, 1, false);
104     set_virtual_reg(vA, OpndSize_64, 2, false);
117     set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
118     set_virtual_reg(vA+1, OpndSize_32, PhysicalReg_EDX, true);
196     set_virtual_reg(vA, OpndSize_32, 1, false);
336     set_virtual_reg(vA, OpndSize_64, 1, false);
346     set_virtual_reg(vA, OpndSize_64, 2, false);
357     set_virtual_reg(vA, OpndSize_64, 3, false);
395     set_virtual_reg(vA, OpndSize_32, 1, false);
408     set_virtual_reg(vA, OpndSize_32, 1, false);
421     set_virtual_reg(vA, OpndSize_32, 1, false);
434     set_virtual_reg(vA, OpndSize_32, 1, false);
449     set_virtual_reg(vA, OpndSize_32, 1, false);
699         set_virtual_reg(vA, OpndSize_32, PhysicalReg_EDX, true);
701         set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
770     set_virtual_reg(vA, OpndSize_32, 1, false);
794     set_virtual_reg(vA, OpndSize_32, 2, false);
1013             set_virtual_reg(vA, OpndSize_32, 1, false);
1027         set_virtual_reg(vA, OpndSize_32, 1, false);
1066         set_virtual_reg(vA, OpndSize_32, PhysicalReg_EDX, true);
1068         set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
1137     set_virtual_reg(vA, OpndSize_64, 1, false);
1270     set_virtual_reg(vA+1, OpndSize_32, 1, false);
1271     set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
1326     set_virtual_reg(vA+1, OpndSize_32,PhysicalReg_EDX, true);
1327     set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
1388     set_virtual_reg(vA, OpndSize_64, 1, false);
1423     set_virtual_reg(vA, OpndSize_64, 1, false);
1832     set_virtual_reg(vA, OpndSize_32, 4, false);
1856     set_virtual_reg(vA, OpndSize_32, 3, false);
1881     set_virtual_reg(vA, OpndSize_32, 4, false);
1907    set_virtual_reg(vA, OpndSize_32, 3, false);
1942     set_virtual_reg(vA, OpndSize_32, 6, false);
1959     set_virtual_reg(vA, OpndSize_32, 6, false);
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