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Lines Matching full:set_virtual_reg

85         set_virtual_reg(vA, OpndSize_64, 1, false);
88 set_virtual_reg(vA, OpndSize_32, 4, false);
468 set_virtual_reg(vA, OpndSize_32, 9, false);
494 set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
495 set_virtual_reg(vA+1, OpndSize_32, PhysicalReg_EDX, true);
498 set_virtual_reg(vA, OpndSize_64, 1, false);
685 set_virtual_reg(vA, OpndSize_32, 7, false);
698 set_virtual_reg(vA, OpndSize_32, PhysicalReg_EAX, true);
699 set_virtual_reg(vA+1, OpndSize_32, PhysicalReg_EDX, true);
703 set_virtual_reg(vA, OpndSize_64, 1, false);
851 set_virtual_reg(vA, OpndSize_32, 2, false);
872 set_virtual_reg(vA, OpndSize_64, 1, false);