Lines Matching refs:LI
212 const LiveInterval &LI);
214 const LiveInterval &LI);
413 const LiveInterval &LI) {
416 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
417 *OS << PrintReg(LI.reg, TRI);
419 *OS << PrintRegUnit(LI.reg, TRI);
420 *OS << ' ' << LI << '\n';
424 const LiveInterval &LI) {
427 if (TargetRegisterInfo::isVirtualRegister(LI.reg))
428 *OS << PrintReg(LI.reg, TRI);
430 *OS << PrintRegUnit(LI.reg, TRI);
431 *OS << ' ' << LI << '\n';
494 for (MachineBasicBlock::livein_iterator LI = MBB->livein_begin(),
496 LI != LE; ++LI) {
497 unsigned reg = *LI;
954 LiveInterval &LI = LiveStks->getInterval(MO->getIndex());
956 if (MI->mayLoad() && !LI.liveAt(Idx.getRegSlot(true))) {
958 *OS << "Live stack: " << LI << '\n';
960 if (MI->mayStore() && !LI.liveAt(Idx.getRegSlot())) {
962 *OS << "Live stack: " << LI << '\n';
997 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(*Units)) {
998 LiveRangeQuery LRQ(*LI, UseIdx);
1002 << ' ' << *LI << '\n';
1006 *OS << PrintRegUnit(*Units, TRI) << ' ' << *LI << '\n';
1015 const LiveInterval &LI = LiveInts->getInterval(Reg);
1016 LiveRangeQuery LRQ(LI, UseIdx);
1019 *OS << UseIdx << " is not live in " << LI << '\n';
1025 *OS << "Live range: " << LI << '\n';
1073 const LiveInterval &LI = LiveInts->getInterval(Reg);
1074 if (const VNInfo *VNI = LI.getVNInfoAt(DefIdx)) {
1079 << DefIdx << " in " << LI << '\n';
1083 *OS << DefIdx << " is not live in " << LI << '\n';
1324 const LiveInterval &LI = LiveInts->getInterval(Reg);
1325 assert(Reg == LI.reg && "Invalid reg to interval mapping");
1326 verifyLiveInterval(LI);
1331 if (const LiveInterval *LI = LiveInts->getCachedRegUnit(i))
1332 verifyLiveInterval(*LI);
1335 void MachineVerifier::verifyLiveIntervalValue(const LiveInterval &LI,
1340 const VNInfo *DefVNI = LI.getVNInfoAt(VNI->def);
1343 report("Valno not live at def and not marked unused", MF, LI);
1349 report("Live range at def has different valno", MF, LI);
1357 report("Invalid definition index", MF, LI);
1359 << " in " << LI << '\n';
1365 report("PHIDef value is not defined at MBB start", MBB, LI);
1375 report("No instruction at def index", MBB, LI);
1385 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1386 if (MOI->getReg() != LI.reg)
1390 !TRI->hasRegUnit(MOI->getReg(), LI.reg))
1400 *OS << "Valno #" << VNI->id << " in " << LI << '\n';
1407 report("Early clobber def must be at an early-clobber slot", MBB, LI);
1412 MBB, LI);
1418 MachineVerifier::verifyLiveIntervalSegment(const LiveInterval &LI,
1423 if (VNI->id >= LI.getNumValNums() || VNI != LI.getValNumInfo(VNI->id)) {
1424 report("Foreign valno in live range", MF, LI);
1429 report("Live range valno is marked unused", MF, LI);
1435 report("Bad start of live segment, no basic block", MF, LI);
1441 report("Live segment must begin at MBB entry or valno def", MBB, LI);
1448 report("Bad end of live segment, no basic block", MF, LI);
1458 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) && VNI->isPHIDef() &&
1466 report("Live segment doesn't end at a valid instruction", EndMBB, LI);
1473 report("Live segment ends at B slot of an instruction", EndMBB, LI);
1481 report("Live segment ending at dead slot spans instructions", EndMBB, LI);
1489 if (I+1 == LI.end() || (I+1)->start != I->end) {
1491 "redefined by an EC def in the same instruction", EndMBB, LI);
1498 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1504 if (!MOI->isReg() || MOI->getReg() != LI.reg)
1516 *OS << " in " << LI << '\n';
1521 *OS << *I << " in " << LI << '\n';
1537 assert(LiveInts->isLiveInToMBB(LI, MFI));
1539 if (!TargetRegisterInfo::isVirtualRegister(LI.reg) &&
1555 const VNInfo *PVNI = LI.getVNInfoBefore(PEnd);
1559 report("Register not marked live out of predecessor", *PI, LI);
1568 report("Different value live out of predecessor", *PI, LI);
1581 void MachineVerifier::verifyLiveInterval(const LiveInterval &LI) {
1582 for (LiveInterval::const_vni_iterator I = LI.vni_begin(), E = LI.vni_end();
1584 verifyLiveIntervalValue(LI, *I);
1586 for (LiveInterval::const_iterator I = LI.begin(), E = LI.end(); I!=E; ++I)
1587 verifyLiveIntervalSegment(LI, I);
1589 // Check the LI only has one connected component.
1590 if (TargetRegisterInfo::isVirtualRegister(LI.reg)) {
1592 unsigned NumComp = ConEQ.Classify(&LI);
1594 report("Multiple connected components in live interval", MF, LI);
1597 for (LiveInterval::const_vni_iterator I = LI.vni_begin(),
1598 E = LI.vni_end(); I!=E; ++I)
