Lines Matching refs:VT
90 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
94 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
184 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
187 unsigned NumMaskElts = VT.getVectorNumElements();
258 EVT VT = CFP->getValueType(0);
261 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
263 (VT == MVT::f64) ? MVT::i64 : MVT::i32);
266 EVT OrigVT = VT;
267 EVT SVT = VT;
277 VT = SVT;
289 VT, false, false, Alignment);
308 EVT VT = Val.getValueType();
313 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits());
391 // Get the half-size VT
400 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount);
429 EVT VT = LD->getValueType(0);
432 if (VT.isFloatingPoint() || VT.isVector()) {
442 if (LoadedVT != VT)
443 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND :
444 ISD::ANY_EXTEND, dl, VT, Result);
504 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase,
515 // Compute the new VT that is half the size of the old one. This is an
533 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
538 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr,
543 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(),
548 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
557 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
558 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
584 EVT VT = Tmp1.getValueType();
585 EVT EltVT = VT.getVectorElementType();
588 SDValue StackPtr = DAG.CreateStackTemporary(VT);
608 return DAG.getLoad(VT, dl, Ch, StackPtr,
716 MVT VT = Value.getSimpleValueType();
717 switch (TLI.getOperationAction(ISD::STORE, VT)) {
737 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
738 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
870 MVT VT = Node->getSimpleValueType(0);
874 switch (TLI.getOperationAction(Node->getOpcode(), VT)) {
897 MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
898 assert(NVT.getSizeInBits() == VT.getSizeInBits() &&
904 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res);
1450 EVT VT = Node->getValueType(0);
1451 EVT EltVT = VT.getVectorElementType();
1453 SDValue FIPtr = DAG.CreateStackTemporary(VT);
1492 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo,
1563 EVT VT = Node->getValueType(0);
1574 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
1579 SP = DAG.getNode(ISD::AND, dl, VT, SP,
1580 DAG.getConstant(-(uint64_t)Align, VT));
1581 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1594 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
1655 LHS = DAG.getSetCC(dl, VT, RHS, LHS, InvCC);
1665 SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1);
1666 SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2);
1669 SetCC1 = DAG.getSetCC(dl, VT, LHS, LHS, CC1);
1670 SetCC2 = DAG.getSetCC(dl, VT, RHS, RHS, CC2);
1672 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2);
1753 EVT VT = Node->getValueType(0);
1755 EVT EltVT = VT.getVectorElementType();
1782 return DAG.getUNDEF(VT);
1785 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0));
1815 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
1830 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1);
1833 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2);
1835 Vec2 = DAG.getUNDEF(VT);
1838 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data());
2498 EVT VT = Op.getValueType();
2499 EVT SHVT = TLI.getShiftAmountTy(VT);
2501 switch (VT.getSimpleVT().SimpleTy) {
2504 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2505 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2506 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
2508 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2509 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2510 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2511 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2512 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT));
2513 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT));
2514 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2515 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2516 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2518 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
2519 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
2520 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
2521 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
2522 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
2523 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT));
2524 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT));
2525 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT));
2526 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT));
2527 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT));
2528 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT));
2529 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT));
2530 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT));
2531 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT));
2532 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7);
2533 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5);
2534 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
2535 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
2536 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6);
2537 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
2538 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4);
2549 EVT VT = Op.getValueType();
2550 EVT ShVT = TLI.getShiftAmountTy(VT);
2551 unsigned Len = VT.getSizeInBits();
2553 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 &&
2559 SDValue Mask55 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x55)), VT);
2560 SDValue Mask33 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x33)), VT);
2561 SDValue Mask0F = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x0F)), VT);
2562 SDValue Mask01 = DAG.getConstant(APInt::getSplat(Len, APInt(8, 0x01)), VT);
2565 Op = DAG.getNode(ISD::SUB, dl, VT, Op,
2566 DAG.getNode(ISD::AND, dl, VT,
2567 DAG.getNode(ISD::SRL, dl, VT, Op,
2571 Op = DAG.getNode(ISD::ADD, dl, VT,
2572 DAG.getNode(ISD::AND, dl, VT, Op, Mask33),
2573 DAG.getNode(ISD::AND, dl, VT,
2574 DAG.getNode(ISD::SRL, dl, VT, Op,
2578 Op = DAG.getNode(ISD::AND, dl, VT,
2579 DAG.getNode(ISD::ADD, dl, VT, Op,
2580 DAG.getNode(ISD::SRL, dl, VT, Op,
2584 Op = DAG.getNode(ISD::SRL, dl, VT,
2585 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01),
2603 EVT VT = Op.getValueType();
2604 EVT ShVT = TLI.getShiftAmountTy(VT);
2605 unsigned len = VT.getSizeInBits();
2608 Op = DAG.getNode(ISD::OR, dl, VT, Op,
2609 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3));
2611 Op = DAG.getNOT(dl, Op, VT);
2612 return DAG.getNode(ISD::CTPOP, dl, VT, Op);
2622 EVT VT = Op.getValueType();
2623 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
2624 DAG.getNOT(dl, Op, VT),
2625 DAG.getNode(ISD::SUB, dl, VT, Op,
2626 DAG.getConstant(1, VT)));
2628 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) &&
2629 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT))
2630 return DAG.getNode(ISD::SUB, dl, VT,
2631 DAG.getConstant(VT.getSizeInBits(), VT),
2632 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3));
2633 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3);
2640 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT();
2647 switch (VT.SimpleTy) {
2656 switch (VT.SimpleTy) {
2665 switch (VT.SimpleTy) {
2674 switch (VT.SimpleTy) {
2683 switch (VT.SimpleTy) {
2692 switch (VT.SimpleTy) {
2701 switch (VT.SimpleTy) {
2710 switch (VT.SimpleTy) {
2835 EVT VT = Node->getValueType(0);
2836 if (VT.isInteger())
2837 Results.push_back(DAG.getConstant(0, VT));
2839 assert(VT.isFloatingPoint() && "Unknown value type!");
2840 Results.push_back(DAG.getConstantFP(0, VT));
2876 EVT VT = Node->getValueType(0);
2877 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT);
2878 if (VT.isVector())
2879 ShiftAmountTy = VT;
2880 unsigned BitsDiff = VT.getScalarType().getSizeInBits() -
2910 EVT VT = Node->getOperand(0).getValueType();
2912 APFloat apf(DAG.EVTToAPFloatSemantics(VT),
2913 APInt::getNullValue(VT.getSizeInBits()));
2916 Tmp1 = DAG.getConstantFP(apf, VT);
2917 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT),
2922 DAG.getNode(ISD::FSUB, dl, VT,
2932 EVT VT = Node->getValueType(0);
2957 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())),
2963 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
3012 EVT VT = Node->getValueType(0);
3013 EVT EltVT = VT.getVectorElementType();
3028 // Calculate new VT, the size of the new VT should be equal to original.
3030 VT.getSizeInBits()/NewEltVT.getSizeInBits());
3031 assert(NewVT.bitsEq(VT));
3033 // cast operands to new VT
3038 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements();
3043 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) {
3054 VT = NewVT;
3058 unsigned NumElems = VT.getVectorNumElements();
3076 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size());
3132 EVT VT = Node->getValueType(0);
3134 Tmp2 = DAG.getConstantFP(0.0, VT);
3137 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1);
3138 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3);
3149 EVT VT = Node->getValueType(0);
3153 if ((TLI.isOperationLegalOrCustom(ISD::FSINCOS, VT) ||
3156 SDVTList VTs = DAG.getVTList(VT, VT);
3284 EVT VT = Node->getValueType(0);
3285 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) &&
3286 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) &&
3288 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1));
3289 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1);
3294 EVT VT = Node->getValueType(0);
3295 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
3296 TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
3298 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1),
3299 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
3300 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT));
3301 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1));
3306 EVT VT = Node->getValueType(0);
3312 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3317 SDVTList VTs = DAG.getVTList(VT, VT);
3319 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) {
3321 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3);
3322 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3);
3323 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1);
3341 EVT VT = Node->getValueType(0);
3342 SDVTList VTs = DAG.getVTList(VT, VT);
3343 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) ||
3365 EVT VT = Node->getValueType(0);
3366 SDVTList VTs = DAG.getVTList(VT, VT);
3367 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
3380 EVT VT = Node->getValueType(0);
3381 SDVTList VTs = DAG.getVTList(VT, VT);
3387 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT);
3388 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT);
3389 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT);
3390 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT);
3462 EVT VT = Node->getValueType(0);
3463 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2);
3472 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) {
3473 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS);
3474 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS);
3475 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) {
3476 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
3480 VT.getSizeInBits() * 2))) {
3484 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3486 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1,
3506 unsigned LoSize = VT.getSizeInBits();
3507 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS,
3509 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS,
3518 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3520 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret,
3529 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1,
3531 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1);
3532 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1,
3535 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf,
3536 DAG.getConstant(0, VT), ISD::SETNE);
3634 EVT VT = Node->getValueType(0);
3636 switch (TLI.getBooleanContents(VT.isVector())) {
3645 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
3646 DAG.getConstant(TrueValue, VT), DAG.getConstant(0, VT),
3693 EVT VT = Node->getValueType(0);
3694 assert(VT.isVector() && "Unable to legalize non-vector shift");
3695 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal");
3696 unsigned NumElem = VT.getVectorNumElements();
3701 VT.getScalarType(),
3704 VT.getScalarType(),
3707 VT.getScalarType(), Ex, Sh));
3764 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT))
