Lines Matching refs:VT
102 void TargetLowering::softenSetCCOperands(SelectionDAG &DAG, EVT VT,
106 assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
114 LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
115 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
119 LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 :
120 (VT == MVT::f64) ? RTLIB::UNE_F64 : RTLIB::UNE_F128;
124 LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
125 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
129 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
130 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
134 LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
135 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
139 LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
140 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
143 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
144 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
147 LC1 = (VT == MVT::f32) ? RTLIB::O_F32 :
148 (VT == MVT::f64) ? RTLIB::O_F64 : RTLIB::O_F128;
151 LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 :
152 (VT == MVT::f64) ? RTLIB::UO_F64 : RTLIB::UO_F128;
156 LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
157 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
160 LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 :
161 (VT == MVT::f64) ? RTLIB::OGT_F64 : RTLIB::OGT_F128;
164 LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 :
165 (VT == MVT::f64) ? RTLIB::OGE_F64 : RTLIB::OGE_F128;
168 LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 :
169 (VT == MVT::f64) ? RTLIB::OLT_F64 : RTLIB::OLT_F128;
172 LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 :
173 (VT == MVT::f64) ? RTLIB::OLE_F64 : RTLIB::OLE_F128;
176 LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 :
177 (VT == MVT::f64) ? RTLIB::OEQ_F64 : RTLIB::OEQ_F128;
282 EVT VT = Op.getValueType();
283 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
286 VT));
297 /// ShrinkDemandedOp - Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the
513 EVT VT = Op.getValueType();
514 SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
515 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
528 EVT VT = Op.getValueType();
529 SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
530 TLO.DAG.getConstant(Expanded, VT));
604 EVT VT = Op.getValueType();
605 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
643 EVT VT = Op.getValueType();
645 unsigned VTSize = VT.getSizeInBits();
668 return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
696 EVT VT = Op.getValueType();
709 InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits());
724 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT,
931 EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
933 VT.getSizeInBits());
1067 TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
1076 case ISD::SETFALSE2: return DAG.getConstant(0, VT);
1078 case ISD::SETTRUE2: return DAG.getConstant(1, VT);
1084 return DAG.getSetCC(dl, VT, N1, N0, ISD::getSetCCSwappedOperands(Cond));
1109 return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0),
1132 return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, CTVT), CC);
1169 return DAG.getSetCC(dl, VT, Trunc, C, Cond);
1223 return DAG.getSetCC(dl, VT,
1243 case ISD::SETEQ: return DAG.getConstant(0, VT);
1246 case ISD::SETNE: return DAG.getConstant(1, VT);
1250 return DAG.getConstant(C1.isNegative(), VT);
1254 return DAG.getConstant(C1.isNonNegative(), VT);
1272 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1290 return DAG.getConstant(Cond == ISD::SETNE, VT);
1304 return DAG.getSetCC(dl, VT, ZextOp,
1314 isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) {
1317 return DAG.getNode(ISD::TRUNCATE, dl, VT, N0);
1322 return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC);
1350 return DAG.getSetCC(dl, VT, Val, N1,
1354 (VT == MVT::i1 ||
1365 return DAG.getSetCC(dl, VT, Op0.getOperand(0), Op0.getOperand(1),
1372 if (Op0.getValueType().bitsGT(VT))
1373 Op0 = DAG.getNode(ISD::AND, dl, VT,
1374 DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)),
1375 DAG.getConstant(1, VT));
1376 else if (Op0.getValueType().bitsLT(VT))
1377 Op0 = DAG.getNode(ISD::AND, dl, VT,
1378 DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)),
1379 DAG.getConstant(1, VT));
1381 return DAG.getSetCC(dl, VT, Op0,
1387 return DAG.getSetCC(dl, VT, Op0,
1405 if (C1 == MinVal) return DAG.getConstant(1, VT); // X >= MIN --> true
1407 return DAG.getSetCC(dl, VT, N0,
1413 if (C1 == MaxVal) return DAG.getConstant(1, VT); // X <= MAX --> true
1415 return DAG.getSetCC(dl, VT, N0,
1421 return DAG.getConstant(0, VT); // X < MIN --> false
1423 return DAG.getConstant(1, VT); // X >= MIN --> true
1425 return DAG.getConstant(0, VT); // X > MAX --> false
1427 return DAG.getConstant(1, VT); // X <= MAX --> true
1431 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1434 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE);
1438 return DAG.getSetCC(dl, VT, N0,
1443 return DAG.getSetCC(dl, VT, N0,
1453 return DAG.getSetCC(dl, VT, N0,
1463 return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT);
1468 (VT == N0.getValueType() ||
1469 (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
1478 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1486 return DAG.getNode(ISD::TRUNCATE, dl, VT,
1509 return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond);
1537 return DAG.getSetCC(dl, VT, Shift, CmpRHS, NewCond);
1545 SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl);
1555 return DAG.getConstant(0, VT);
1557 return DAG.getConstant(1, VT);
1559 return DAG.getUNDEF(VT);
1568 return DAG.getSetCC(dl, VT, N0, N0, Cond);
1580 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLE);
1583 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULE);
1586 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGT);
1589 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGT);
1593 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOGE);
1596 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETUGE);
1599 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETULT);
1602 return DAG.getSetCC(dl, VT, N0, N1, ISD::SETOLT);
1624 return DAG.getConstant(EqVal, VT);
1628 return DAG.getConstant(EqVal, VT);
1630 return DAG.getConstant(EqVal, VT);
1636 return DAG.getSetCC(dl, VT, N0, N1, NewCond);
1646 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(1), Cond);
1648 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(0), Cond);
1652 return DAG.getSetCC(dl, VT, N0.getOperand(1), N1.getOperand(0),
1655 return DAG.getSetCC(dl, VT, N0.getOperand(0), N1.getOperand(1),
1668 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1680 DAG.getSetCC(dl, VT, N0.getOperand(0),
1691 DAG.getSetCC(dl, VT, N0.getOperand(1),
1710 return DAG.getSetCC(dl, VT, N0.getOperand(1),
1714 return DAG.getSetCC(dl, VT, N0.getOperand(0),
1723 return DAG.getSetCC(dl, VT, N0.getOperand(0), SH, Cond);
1733 return DAG.getSetCC(dl, VT, N1.getOperand(1),
1737 return DAG.getSetCC(dl, VT, N1.getOperand(0),
1746 return DAG.getSetCC(dl, VT, SH, N1.getOperand(0), Cond);
1760 return DAG.getSetCC(dl, VT, N0, Zero, Cond);
1768 return DAG.getSetCC(dl, VT, N1, Zero, Cond);
1814 if (VT != MVT::i1) {
1818 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0);
1992 EVT VT) const {
2023 if (RC->hasType(VT))
2471 EVT VT = N->getValueType(0);
2476 if (!isTypeLegal(VT))
2485 if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) :
2486 isOperationLegalOrCustom(ISD::MULHS, VT))
2487 Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0),
2488 DAG.getConstant(magics.m, VT));
2489 else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) :
2490 isOperationLegalOrCustom(ISD::SMUL_LOHI, VT))
2491 Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT),
2493 DAG.getConstant(magics.m, VT)).getNode(), 1);
2498 Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0));
2504 Q = DAG.getNode(ISD::SUB, dl, VT, Q, N->getOperand(0));
2510 Q = DAG.getNode(ISD::SRA, dl, VT, Q,
2517 DAG.getNode(ISD::SRL, dl, VT, Q, DAG.getConstant(VT.getSizeInBits()-1,
2521 return DAG.getNode(ISD::ADD, dl, VT, Q, T);
2531 EVT VT = N->getValueType(0);
2536 if (!isTypeLegal(VT))
2550 Q = DAG.getNode(ISD::SRL, dl, VT, Q,
2562 if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) :
2563 isOperationLegalOrCustom(ISD::MULHU, VT))
2564 Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, VT));
2565 else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) :
2566 isOperationLegalOrCustom(ISD::UMUL_LOHI, VT))
2567 Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q,
2568 DAG.getConstant(magics.m, VT)).getNode(), 1);
2577 return DAG.getNode(ISD::SRL, dl, VT, Q,
2580 SDValue NPQ = DAG.getNode(ISD::SUB, dl, VT, N->getOperand(0), Q);
2583 NPQ = DAG.getNode(ISD::SRL, dl, VT, NPQ,
2587 NPQ = DAG.getNode(ISD::ADD, dl, VT, NPQ, Q);
2590 return DAG.getNode(ISD::SRL, dl, VT, NPQ,
