Lines Matching refs:AArch64
1 //===- AArch64FrameLowering.cpp - AArch64 Frame Information ---------------===//
10 // This file contains the AArch64 implementation of TargetFrameLowering class.
14 #include "AArch64.h"
89 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumInitialBytes,
100 MachineLocation Src(AArch64::XSP, NumInitialBytes);
113 if (FPNeedsSetting && MBBI->getOpcode() == AArch64::LSPair64_STR
114 && MBBI->getOperand(0).getReg() == AArch64::X29) {
119 emitRegUpdate(MBB, MBBI, DL, TII, AArch64::X29, AArch64::XSP,
120 AArch64::X29,
125 // to whatever frame base is set. AArch64 uses the default frame base (FP
135 MachineLocation Src(AArch64::X29, -MFI->getObjectOffset(X29FrameIdx));
148 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16, -NumResidualBytes,
167 MachineLocation Src(AArch64::XSP, NumResidualBytes + NumInitialBytes);
208 if (RetOpcode == AArch64::TC_RETURNdi ||
209 RetOpcode == AArch64::TC_RETURNxi) {
214 if (RetOpcode == AArch64::TC_RETURNdi) {
215 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_Bimm));
225 assert(RetOpcode == AArch64::TC_RETURNxi && JumpTarget.isReg()
228 MIB = BuildMI(MBB, MBBI, DL, TII.get(AArch64::TAIL_BRx));
273 emitSPUpdate(MBB, MBBI, DL, TII, AArch64::X16,
311 AArch64::XSP, AArch64::X29, AArch64::NoRegister,
314 emitSPUpdate(MBB, FirstEpilogue, DL,TII, AArch64::X16, NumResidualBytes);
338 FrameReg = AArch64::XSP;
342 FrameReg = AArch64::X29;
345 FrameReg = AArch64::XSP;
362 MF.getRegInfo().setPhysRegUsed(AArch64::X29);
363 MF.getRegInfo().setPhysRegUsed(AArch64::X30);
382 uint16_t ExtraReg = AArch64::NoRegister;
385 if (AArch64::GPR64RegClass.contains(CSRegs[i]) &&
398 const TargetRegisterClass *RC = &AArch64::GPR64RegClass;
409 if (Reg == AArch64::X30) {
530 {&AArch64::GPR64RegClass, AArch64::LSPair64_STR, AArch64::LS64_STR},
531 {&AArch64::FPR64RegClass, AArch64::LSFPPair64_STR, AArch64::LSFP64_STR},
551 {&AArch64::GPR64RegClass, AArch64::LSPair64_LDR, AArch64::LS64_LDR},
552 {&AArch64::FPR64RegClass, AArch64::LSFPPair64_LDR, AArch64::LSFP64_LDR},
567 // This is a decision of ABI compliance. The AArch64 PCS gives various options
623 emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, Amount);
629 emitSPUpdate(MBB, MI, dl, TII, AArch64::NoRegister, -CalleePopAmount);
