Lines Matching refs:AArch64
1 //===- AArch64InstrInfo.cpp - AArch64 Instruction Information -------------===//
10 // This file contains the AArch64 implementation of the TargetInstrInfo class.
14 #include "AArch64.h"
38 : AArch64GenInstrInfo(AArch64::ADJCALLSTACKDOWN, AArch64::ADJCALLSTACKUP),
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) {
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg)
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) {
55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg)
59 } else if (DestReg == AArch64::NZCV) {
60 assert(AArch64::GPR64RegClass.contains(SrcReg));
62 BuildMI(MBB, I, DL, get(AArch64::MSRix))
65 } else if (SrcReg == AArch64::NZCV) {
66 assert(AArch64::GPR64RegClass.contains(DestReg));
68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg)
70 } else if (AArch64::GPR64RegClass.contains(DestReg)) {
71 assert(AArch64::GPR64RegClass.contains(SrcReg));
72 Opc = AArch64::ORRxxx_lsl;
73 ZeroReg = AArch64::XZR;
74 } else if (AArch64::GPR32RegClass.contains(DestReg)) {
75 assert(AArch64::GPR32RegClass.contains(SrcReg));
76 Opc = AArch64::ORRwww_lsl;
77 ZeroReg = AArch64::WZR;
78 } else if (AArch64::FPR32RegClass.contains(DestReg)) {
79 assert(AArch64::FPR32RegClass.contains(SrcReg));
80 BuildMI(MBB, I, DL, get(AArch64::FMOVss), DestReg)
83 } else if (AArch64::FPR64RegClass.contains(DestReg)) {
84 assert(AArch64::FPR64RegClass.contains(SrcReg));
85 BuildMI(MBB, I, DL, get(AArch64::FMOVdd), DestReg)
88 } else if (AArch64::FPR128RegClass.contains(DestReg)) {
89 assert(AArch64::FPR128RegClass.contains(SrcReg));
98 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PreInd_STR), AArch64::XSP)
100 .addReg(AArch64::XSP)
103 BuildMI(MBB, I, DL, get(AArch64::LSFP128_PostInd_LDR), DestReg)
104 .addReg(AArch64::XSP, RegState::Define)
105 .addReg(AArch64::XSP)
123 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AArch64::DBG_VALUE))
133 return Opc == AArch64::Bcc || Opc == AArch64::CBZw || Opc == AArch64::CBZx ||
134 Opc == AArch64::CBNZw || Opc == AArch64::CBNZx ||
135 Opc == AArch64::TBZwii || Opc == AArch64::TBZxii ||
136 Opc == AArch64::TBNZwii || Opc == AArch64::TBNZxii;
147 case AArch64::Bcc:
148 case AArch64::CBZw:
149 case AArch64::CBZx:
150 case AArch64::CBNZw:
151 case AArch64::CBNZx:
158 case AArch64::TBZwii:
159 case AArch64::TBZxii:
160 case AArch64::TBNZwii:
161 case AArch64::TBNZxii:
198 if (LastOpc == AArch64::Bimm) {
215 if (AllowModify && LastOpc == AArch64::Bimm) {
216 while (SecondLastOpc == AArch64::Bimm) {
236 if (LastOpc == AArch64::Bimm) {
237 if (SecondLastOpc == AArch64::Bcc) {
239 Cond.push_back(MachineOperand::CreateImm(AArch64::Bcc));
252 if (SecondLastOpc == AArch64::Bimm && LastOpc == AArch64::Bimm) {
267 case AArch64::Bcc: {
273 case AArch64::CBZw:
274 Cond[0].setImm(AArch64::CBNZw);
276 case AArch64::CBZx:
277 Cond[0].setImm(AArch64::CBNZx);
279 case AArch64::CBNZw:
280 Cond[0].setImm(AArch64::CBZw);
282 case AArch64::CBNZx:
283 Cond[0].setImm(AArch64::CBZx);
285 case AArch64::TBZwii:
286 Cond[0].setImm(AArch64::TBNZwii);
288 case AArch64::TBZxii:
289 Cond[0].setImm(AArch64::TBNZxii);
291 case AArch64::TBNZwii:
292 Cond[0].setImm(AArch64::TBZwii);
294 case AArch64::TBNZxii:
295 Cond[0].setImm(AArch64::TBZxii);
309 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(TBB);
324 BuildMI(&MBB, DL, get(AArch64::Bimm)).addMBB(FBB);
337 if (I->getOpcode() != AArch64::Bimm && !isCondBranch(I->getOpcode()))
362 case AArch64::TLSDESC_BLRx: {
364 BuildMI(MBB, MBBI, MI.getDebugLoc(), get(AArch64::TLSDESCCALL))
366 MI.setDesc(get(AArch64::BLRx));
399 case 4: StoreOp = AArch64::LS32_STR; break;
400 case 8: StoreOp = AArch64::LS64_STR; break;
409 case 4: StoreOp = AArch64::LSFP32_STR; break;
410 case 8: StoreOp = AArch64::LSFP64_STR; break;
411 case 16: StoreOp = AArch64::LSFP128_STR; break;
445 case 4: LoadOp = AArch64::LS32_LDR; break;
446 case 8: LoadOp = AArch64::LS64_LDR; break;
455 case 4: LoadOp = AArch64::LSFP32_LDR; break;
456 case 8: LoadOp = AArch64::LSFP64_LDR; break;
457 case 16: LoadOp = AArch64::LSFP128_LDR; break;
479 if (I->getOpcode() == AArch64::ADDxxi_lsl0_s) {
505 case AArch64::LS8_LDR: case AArch64::LS8_STR:
506 case AArch64::LSFP8_LDR: case AArch64::LSFP8_STR:
507 case AArch64::LDRSBw:
508 case AArch64::LDRSBx:
513 case AArch64::LS16_LDR: case AArch64::LS16_STR:
514 case AArch64::LSFP16_LDR: case AArch64::LSFP16_STR:
515 case AArch64::LDRSHw:
516 case AArch64::LDRSHx:
521 case AArch64::LS32_LDR: case AArch64::LS32_STR:
522 case AArch64::LSFP32_LDR: case AArch64::LSFP32_STR:
523 case AArch64::LDRSWx:
524 case AArch64::LDPSWx:
529 case AArch64::LS64_LDR: case AArch64::LS64_STR:
530 case AArch64::LSFP64_LDR: case AArch64::LSFP64_STR:
531 case AArch64::PRFM:
536 case AArch64::LSFP128_LDR: case AArch64::LSFP128_STR:
541 case AArch64::LSPair32_LDR: case AArch64::LSPair32_STR:
542 case AArch64::LSFPPair32_LDR: case AArch64::LSFPPair32_STR:
547 case AArch64::LSPair64_LDR: case AArch64::LSPair64_STR:
548 case AArch64::LSFPPair64_LDR: case AArch64::LSFPPair64_STR:
553 case AArch64::LSFPPair128_LDR: case AArch64::LSFPPair128_STR:
570 if (MI.getOpcode() == AArch64::INLINEASM)
585 case AArch64::TLSDESCCALL:
626 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVZxii), ScratchReg)
632 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
640 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
648 BuildMI(MBB, MBBI, dl, TII.get(AArch64::MOVKxii), ScratchReg)
655 unsigned AddOp = NumBytes > 0 ? AArch64::ADDxxx_uxtx : AArch64::SUBxxx_uxtx;
671 LowOp = AArch64::ADDxxi_lsl0_s;
672 HighOp = AArch64::ADDxxi_lsl12_s;
674 LowOp = AArch64::SUBxxi_lsl0_s;
675 HighOp = AArch64::SUBxxi_lsl12_s;
703 emitRegUpdate(MBB, MI, dl, TII, AArch64::XSP, AArch64::XSP, AArch64::X16,
738 case AArch64::TLSDESC_BLRx:
777 AArch64::X0)
796 *TLSBaseAddrReg = RegInfo.createVirtualRegister(&AArch64::GPR64RegClass);
803 .addReg(AArch64::X0);
