Lines Matching defs:Ops
1469 SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
1472 MVT::i32, MVT::Other, Ops, 5);
1476 SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
1479 MVT::i32, MVT::Other, Ops, 6);
1525 SDValue Ops[]= { Base, Offset, getAL(CurDAG),
1528 MVT::Other, Ops, 5);
1541 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1542 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1552 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1553 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1562 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1563 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1572 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 };
1573 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 5);
1586 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1588 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1600 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1602 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1614 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1,
1616 return CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, dl, VT, Ops, 9);
1741 SmallVector<SDValue, 7> Ops;
1747 Ops.push_back(MemAddr);
1748 Ops.push_back(Align);
1759 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1761 Ops.push_back(Pred);
1762 Ops.push_back(Reg0);
1763 Ops.push_back(Chain);
1764 Ops.data(), Ops.size());
1781 Ops.push_back(SDValue(VLdA, 1));
1782 Ops.push_back(Align);
1788 Ops.push_back(Reg0);
1790 Ops.push_back(SDValue(VLdA, 0));
1791 Ops.push_back(Pred);
1792 Ops.push_back(Reg0);
1793 Ops.push_back(Chain);
1795 Ops.data(), Ops.size());
1867 SmallVector<SDValue, 7> Ops;
1898 Ops.push_back(MemAddr);
1899 Ops.push_back(Align);
1910 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
1912 Ops.push_back(SrcReg);
1913 Ops.push_back(Pred);
1914 Ops.push_back(Reg0);
1915 Ops.push_back(Chain);
1917 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
1947 Ops.push_back(SDValue(VStA, 0));
1948 Ops.push_back(Align);
1954 Ops.push_back(Reg0);
1956 Ops.push_back(RegSeq);
1957 Ops.push_back(Pred);
1958 Ops.push_back(Reg0);
1959 Ops.push_back(Chain);
1961 Ops.data(), Ops.size());
2032 SmallVector<SDValue, 8> Ops;
2033 Ops.push_back(MemAddr);
2034 Ops.push_back(Align);
2037 Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
2058 Ops.push_back(SuperReg);
2059 Ops.push_back(getI32Imm(Lane));
2060 Ops.push_back(Pred);
2061 Ops.push_back(Reg0);
2062 Ops.push_back(Chain);
2067 Ops.data(), Ops.size());
2130 SmallVector<SDValue, 6> Ops;
2131 Ops.push_back(MemAddr);
2132 Ops.push_back(Align);
2138 Ops.push_back(Inc);
2141 Ops.push_back(Reg0);
2143 Ops.push_back(Pred);
2144 Ops.push_back(Reg0);
2145 Ops.push_back(Chain);
2154 CurDAG->getMachineNode(Opc, dl, ResTys, Ops.data(), Ops.size());
2193 SmallVector<SDValue, 6> Ops;
2195 Ops.push_back(N->getOperand(1));
2196 Ops.push_back(RegSeq);
2197 Ops.push_back(N->getOperand(FirstTblReg + NumVecs));
2198 Ops.push_back(getAL(CurDAG)); // predicate
2199 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // predicate register
2200 return CurDAG->getMachineNode(Opc, dl, VT, Ops.data(), Ops.size());
2236 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2239 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2247 SDValue Ops[] = { N->getOperand(0).getOperand(0), ShOpc,
2249 return CurDAG->SelectNodeTo(N, ARM::MOVsi, MVT::i32, Ops, 5);
2252 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2256 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2275 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2279 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2305 SDValue Ops[] = { FalseVal, CPTmp0, SOShImm, CC, CCR, InFlag };
2306 return CurDAG->SelectNodeTo(N, Opc, MVT::i32,Ops, 6);
2319 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp2, CC, CCR, InFlag };
2320 return CurDAG->SelectNodeTo(N, ARM::MOVCCsi, MVT::i32, Ops, 6);
2325 SDValue Ops[] = { FalseVal, CPTmp0, CPTmp1, CPTmp2, CC, CCR, InFlag };
2326 return CurDAG->SelectNodeTo(N, ARM::MOVCCsr, MVT::i32, Ops, 7);
2355 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2356 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2388 SDValue Ops[] = { FalseVal, True, CC, CCR, InFlag };
2389 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2464 SDValue Ops[] = { FalseVal, TrueVal, Tmp2, CCR, InFlag };
2480 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 5);
2532 SmallVector<SDValue, 6> Ops;
2533 Ops.push_back(Node->getOperand(1)); // Ptr
2534 Ops.push_back(Node->getOperand(2)); // Low part of Val1
2535 Ops.push_back(Node->getOperand(3)); // High part of Val1
2537 Ops.push_back(Node->getOperand(4)); // Low part of Val2
2538 Ops.push_back(Node->getOperand(5)); // High part of Val2
2540 Ops.push_back(Node->getOperand(0)); // Chain
2545 Ops.data() ,Ops.size());
2600 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() };
2602 Ops, 4);
2604 SDValue Ops[] = {
2612 Ops, 5);
2626 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2628 return CurDAG->SelectNodeTo(N, ARM::tADDrSPi, MVT::i32, Ops, 4);
2632 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
2635 return CurDAG->SelectNodeTo(N, Opc, MVT::i32, Ops, 5);
2661 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2662 return CurDAG->SelectNodeTo(N, ARM::t2ADDrs, MVT::i32, Ops, 6);
2664 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2665 return CurDAG->SelectNodeTo(N, ARM::ADDrsi, MVT::i32, Ops, 7);
2677 SDValue Ops[] = { V, V, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2678 return CurDAG->SelectNodeTo(N, ARM::t2RSBrs, MVT::i32, Ops, 6);
2680 SDValue Ops[] = { V, V, Reg0, ShImmOp, getAL(CurDAG), Reg0, Reg0 };
2681 return CurDAG->SelectNodeTo(N, ARM::RSBrsi, MVT::i32, Ops, 7);
2720 SDValue Ops[] = { N0.getOperand(0), Imm16,
2722 return CurDAG->getMachineNode(Opc, dl, VT, Ops, 4);
2735 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2738 return CurDAG->getMachineNode(ARM::t2UMULL, dl, MVT::i32, MVT::i32,Ops,4);
2740 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2745 dl, MVT::i32, MVT::i32, Ops, 5);
2752 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2754 return CurDAG->getMachineNode(ARM::t2SMULL, dl, MVT::i32, MVT::i32,Ops,4);
2756 SDValue Ops[] = { N->getOperand(0), N->getOperand(1),
2761 dl, MVT::i32, MVT::i32, Ops, 5);
2766 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2769 return CurDAG->getMachineNode(ARM::t2UMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
2771 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2777 dl, MVT::i32, MVT::i32, Ops, 7);
2782 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2785 return CurDAG->getMachineNode(ARM::t2SMLAL, dl, MVT::i32, MVT::i32, Ops, 6);
2787 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), N->getOperand(2),
2793 dl, MVT::i32, MVT::i32, Ops, 7);
2834 SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
2836 MVT::Glue, Ops, 5);
2865 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2866 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2885 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2886 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
2904 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg };
2905 return CurDAG->getMachineNode(Opc, dl, VT, VT, Ops, 4);
3145 SmallVector<SDValue, 7> Ops;
3146 Ops.push_back(MemAddr);
3147 Ops.push_back(getAL(CurDAG));
3148 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3149 Ops.push_back(Chain);
3150 SDNode *Ld = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3151 Ops.size());
3200 SmallVector<SDValue, 7> Ops;
3202 Ops.push_back(Val0);
3203 Ops.push_back(Val1);
3206 Ops.push_back(SDValue(createGPRPairNode(MVT::Untyped, Val0, Val1), 0));
3207 Ops.push_back(MemAddr);
3208 Ops.push_back(getAL(CurDAG));
3209 Ops.push_back(CurDAG->getRegister(0, MVT::i32));
3210 Ops.push_back(Chain);
3214 SDNode *St = CurDAG->getMachineNode(NewOpc, dl, ResTys, Ops.data(),
3215 Ops.size());
3395 SmallVector<SDValue, 6> Ops;
3397 Ops.push_back(N->getOperand(0));
3398 Ops.push_back(N->getOperand(1));
3399 Ops.push_back(getAL(CurDAG)); // Predicate
3400 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3401 return CurDAG->getMachineNode(ARM::VTBL1, dl, VT, Ops.data(), Ops.size());
3412 SmallVector<SDValue, 6> Ops;
3413 Ops.push_back(RegSeq);
3414 Ops.push_back(N->getOperand(2));
3415 Ops.push_back(getAL(CurDAG)); // Predicate
3416 Ops.push_back(CurDAG->getRegister(0, MVT::i32)); // Predicate Register
3418 Ops.data(), Ops.size());
3532 std::vector<SDValue> Ops(GU->op_begin(), GU->op_end()-1);
3533 Ops.push_back(T1.getValue(1));
3534 CurDAG->UpdateNodeOperands(GU, &Ops[0], Ops.size());
