Lines Matching refs:getOpcode
1749 if (Arg.getOpcode() == ISD::CopyFromReg) {
2034 if (Copy->getOpcode() == ISD::CopyToReg) {
2040 } else if (Copy->getOpcode() == ARMISD::VMOVRRD) {
2046 if (UI->getOpcode() != ISD::CopyToReg)
2063 } else if (Copy->getOpcode() == ISD::BITCAST) {
2068 if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
2078 if (UI->getOpcode() != ARMISD::RET_FLAG)
2831 if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
2917 unsigned Opc = Cmp.getOpcode();
2924 Opc = Cmp.getOpcode();
2945 if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
3236 Op = DAG.getNode(Op.getOpcode(), dl, MVT::v4i32, Op.getOperand(0));
3248 switch (Op.getOpcode()) {
3278 switch (Op.getOpcode()) {
3302 switch (Op.getOpcode()) {
3323 bool InGPR = Tmp0.getOpcode() == ISD::BITCAST ||
3324 Tmp0.getOpcode() == ARMISD::VMOVDRR;
3501 unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
3503 assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
3538 assert(Op.getOpcode() == ISD::SHL_PARTS);
3709 if (N->getOpcode() == ISD::SHL)
3714 assert((N->getOpcode() == ISD::SRA ||
3715 N->getOpcode() == ISD::SRL) && "unexpected vector shift opcode");
3724 Intrinsic::ID vshiftInt = (N->getOpcode() == ISD::SRA ?
3741 assert((N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) &&
3760 unsigned Opc = N->getOpcode() == ISD::SRL ? ARMISD::SRL_FLAG:ARMISD::SRA_FLAG;
3847 if (AndOp.getNode() && AndOp.getOpcode() == ISD::BITCAST)
3850 if (AndOp.getNode() && AndOp.getOpcode() == ISD::AND) {
4418 if (V.getOpcode() == ISD::UNDEF)
4458 if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4558 if (V.getOpcode() == ISD::UNDEF)
4560 else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT) {
4663 if (Entry.getOpcode() == ISD::UNDEF) {
4824 if (V2.getNode()->getOpcode() == ISD::UNDEF)
4874 if (Lane == 0 && V1.getOpcode() == ISD::SCALAR_TO_VECTOR) {
4880 if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
4884 if (V1.getOperand(i).getOpcode() != ISD::UNDEF) {
4911 if (V2->getOpcode() == ISD::UNDEF &&
5034 if (Op0.getOpcode() != ISD::UNDEF)
5038 if (Op1.getOpcode() != ISD::UNDEF)
5052 if (VT == MVT::v2i64 && N->getOpcode() == ISD::BITCAST) {
5055 BVN->getOpcode() != ISD::BUILD_VECTOR)
5076 if (N->getOpcode() != ISD::BUILD_VECTOR)
5102 if (N->getOpcode() == ISD::SIGN_EXTEND || ISD::isSEXTLoad(N))
5112 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N))
5180 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND)
5184 N->getOpcode());
5191 if (N->getOpcode() == ISD::BITCAST) {
5193 assert(BVN->getOpcode() == ISD::BUILD_VECTOR &&
5200 assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
5218 unsigned Opcode = N->getOpcode();
5229 unsigned Opcode = N->getOpcode();
5307 return DAG.getNode(N0->getOpcode(), DL, VT,
5495 switch (Op.getOpcode()) {
5555 switch (Op.getOpcode()) {
5618 switch (N->getOpcode()) {
7010 switch (MI->getOpcode()) {
7030 unsigned NewOpc = MI->getOpcode() == ARM::STRi_preidx ?
7055 switch (MI->getOpcode()) {
7252 bool RHSisZero = MI->getOpcode() == ARM::BCCZi64;
7383 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
7397 unsigned NewOpc = convertAddSubFlagsOpcode(MI->getOpcode());
7480 switch (N->getOpcode()) {
7513 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7562 SDValue FalseVal = DAG.getNode(N->getOpcode(), N->getDebugLoc(), VT,
7600 || N0.getOpcode() != ISD::BUILD_VECTOR
7601 || N1.getOpcode() != ISD::BUILD_VECTOR)
7616 if (N0->getOperand(0)->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
7626 if (N0->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT
7627 && N1->getOperand(i)->getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
7681 if (V->getOpcode() == ISD::UMUL_LOHI ||
7682 V->getOpcode() == ISD::SMUL_LOHI)
7710 assert(AddcNode->getOpcode() == ISD::ADDC && "Expect an ADDC");
7724 if (AddcOp0->getOpcode() != ISD::UMUL_LOHI &&
7725 AddcOp0->getOpcode() != ISD::SMUL_LOHI &&
7726 AddcOp1->getOpcode() != ISD::UMUL_LOHI &&
7727 AddcOp1->getOpcode() != ISD::SMUL_LOHI)
7736 if (AddeNode->getOpcode() != ISD::ADDE)
7762 unsigned Opc = MULOp->getOpcode();
7777 if (AddcOp0->getOpcode() == Opc) {
7781 if (AddcOp1->getOpcode() == Opc) {
7899 unsigned Opcode = N0.getOpcode();
7902 Opcode = N1.getOpcode();
8089 if (N0.getOpcode() != ISD::AND || !N0.hasOneUse())
8094 if (Subtarget->hasNEON() && N1.getOpcode() == ISD::AND && VT.isVector() &&
8171 } else if (N1.getOpcode() == ISD::AND) {
8216 N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
8260 if (N1.getOpcode() == ISD::AND) {
8283 if (InDouble.getOpcode() == ARMISD::VMOVDRR)
8290 InNode->getOperand(1).getOpcode() == ISD::FrameIndex &&
8326 if (Op0.getOpcode() == ISD::BITCAST)
8328 if (Op1.getOpcode() == ISD::BITCAST)
8330 if (Op0.getOpcode() == ARMISD::VMOVRRD &&
8433 if (StVal.getNode()->getOpcode() == ARMISD::VMOVDRR &&
8452 StVal.getNode()->getOpcode() != ISD::EXTRACT_VECTOR_ELT)
8566 if (Op0.getOpcode() != ISD::CONCAT_VECTORS ||
8567 Op1.getOpcode() != ISD::CONCAT_VECTORS ||
8573 if (Concat0Op1.getOpcode() != ISD::UNDEF ||
8574 Concat1Op1.getOpcode() != ISD::UNDEF)
8612 bool isIntrinsic = (N->getOpcode() == ISD::INTRINSIC_VOID ||
8613 N->getOpcode() == ISD::INTRINSIC_W_CHAIN);
8621 if (User->getOpcode() != ISD::ADD ||
8670 switch (N->getOpcode()) {
8749 if (VLD->getOpcode() != ISD::INTRINSIC_W_CHAIN)
8777 if (User->getOpcode() != ARMISD::VDUPLANE ||
8830 while (Op.getOpcode() == ISD::BITCAST)
8832 if (Op.getOpcode() != ARMISD::VMOVIMM && Op.getOpcode() != ARMISD::VMVNIMM)
8891 Op.getOpcode() != ISD::FMUL)
8897 bool isSigned = N->getOpcode() == ISD::FP_TO_SINT;
8899 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8925 unsigned OpOpcode = Op.getNode()->getOpcode();
8935 if (ConstVec.getOpcode() != ISD::BUILD_VECTOR ||
8952 while (Op.getOpcode() == ISD::BITCAST)
9164 if (N->getOpcode() == ISD::SRL && VT == MVT::i32 && ST->hasV6Ops()) {
9170 if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
9185 switch (N->getOpcode()) {
9197 unsigned VShiftOpc = (N->getOpcode() == ISD::SRA ?
9216 if (ST->hasNEON() && N0.getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
9229 switch (N->getOpcode()) {
9335 if (Cmp.getOpcode() != ARMISD::CMPZ)
9397 switch (N->getOpcode()) {
9534 if (Val.getOpcode() != ISD::LOAD)
9778 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9787 assert(Ptr->getOpcode() == ISD::ADD);
9793 isInc = (Ptr->getOpcode() == ISD::ADD);
9801 assert(Ptr->getOpcode() == ISD::ADD);
9809 if (Ptr->getOpcode() == ISD::ADD) {
9812 ARM_AM::getShiftOpcForNode(Ptr->getOperand(0).getOpcode());
9823 isInc = (Ptr->getOpcode() == ISD::ADD);
9837 if (Ptr->getOpcode() != ISD::ADD && Ptr->getOpcode() != ISD::SUB)
9844 assert(Ptr->getOpcode() == ISD::ADD);
9849 isInc = Ptr->getOpcode() == ISD::ADD;
9935 getOpcode() == ISD::ADD &&
9954 switch (Op.getOpcode()) {
