Cross Reference: /external/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp

Lines Matching refs:getOpcode
72   switch (MI->getOpcode()) {
97   switch (MI->getOpcode()) {
215     if (LastInst->getOpcode() == Hexagon::JMP) {
219     if (LastInst->getOpcode() == Hexagon::JMP_c) {
225     if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
245   if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246       (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247       LastInst->getOpcode() == Hexagon::JMP) {
255   if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256       LastInst->getOpcode() == Hexagon::JMP) {
266   if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267       LastInst->getOpcode() == Hexagon::JMP) {
288   if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289       I->getOpcode() != BccOpcNot)
299   if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
315   unsigned Opc = MI->getOpcode();
571   switch(MI->getOpcode()) {
600   switch (MI->getOpcode()) {
706   switch (MI->getOpcode()) {
826   switch (MI->getOpcode())
913   return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
922   const int Opc = MI->getOpcode();
1712   int Opc = MI->getOpcode();
1932   switch (MI->getOpcode()) {
2086   switch (MI->getOpcode())
2132   switch (MI->getOpcode()) {
2141   switch (MI->getOpcode()) {
2159   switch (MI->getOpcode()) {
2175   switch (MI->getOpcode())
2212   switch (MI->getOpcode())
2306   switch (MI->getOpcode())
2533   if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2543       NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
2549       NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2566   short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2574       return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2576       return Hexagon::getBaseWithRegOffset(MI->getOpcode());
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