Lines Matching refs:MBlaze
1 //===-- MBlazeISelLowering.cpp - MBlaze DAG Lowering Implementation -------===//
10 // This file defines the interfaces that MBlaze uses to lower LLVM code into a
15 #define DEBUG_TYPE "mblaze-lower"
59 // MBlaze does not have i1 type, so use i32 for
65 addRegisterClass(MVT::i32, &MBlaze::GPRRegClass);
67 addRegisterClass(MVT::f32, &MBlaze::GPRRegClass);
101 // MBlaze has no REM or DIVREM operations.
133 // MBlaze doesn't have MUL_LOHI
147 // MBlaze Custom Operations
160 // Operations not directly supported by MBlaze.
185 // MBlaze doesn't have extending float->double load/store
191 setStackPointerRegisterToSaveRestore(MBlaze::R1);
223 case MBlaze::ShiftRL:
224 case MBlaze::ShiftRA:
225 case MBlaze::ShiftL:
228 case MBlaze::Select_FCC:
229 case MBlaze::Select_CC:
232 case MBlaze::CAS32:
233 case MBlaze::SWP32:
234 case MBlaze::LAA32:
235 case MBlaze::LAS32:
236 case MBlaze::LAD32:
237 case MBlaze::LAO32:
238 case MBlaze::LAX32:
239 case MBlaze::LAN32:
242 case MBlaze::MEMBARRIER:
296 unsigned IAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
297 BuildMI(MBB, dl, TII->get(MBlaze::ANDI), IAMT)
301 unsigned IVAL = R.createVirtualRegister(&MBlaze::GPRRegClass);
302 BuildMI(MBB, dl, TII->get(MBlaze::ADDIK), IVAL)
306 BuildMI(MBB, dl, TII->get(MBlaze::BEQID))
310 unsigned DST = R.createVirtualRegister(&MBlaze::GPRRegClass);
311 unsigned NDST = R.createVirtualRegister(&MBlaze::GPRRegClass);
312 BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
316 unsigned SAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
317 unsigned NAMT = R.createVirtualRegister(&MBlaze::GPRRegClass);
318 BuildMI(loop, dl, TII->get(MBlaze::PHI), SAMT)
322 if (MI->getOpcode() == MBlaze::ShiftL)
323 BuildMI(loop, dl, TII->get(MBlaze::ADD), NDST).addReg(DST).addReg(DST);
324 else if (MI->getOpcode() == MBlaze::ShiftRA)
325 BuildMI(loop, dl, TII->get(MBlaze::SRA), NDST).addReg(DST);
326 else if (MI->getOpcode() == MBlaze::ShiftRL)
327 BuildMI(loop, dl, TII->get(MBlaze::SRL), NDST).addReg(DST);
331 BuildMI(loop, dl, TII->get(MBlaze::ADDIK), NAMT)
335 BuildMI(loop, dl, TII->get(MBlaze::BNEID))
340 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
376 case MBlazeCC::EQ: Opc = MBlaze::BEQID; break;
377 case MBlazeCC::NE: Opc = MBlaze::BNEID; break;
378 case MBlazeCC::GT: Opc = MBlaze::BGTID; break;
379 case MBlazeCC::LT: Opc = MBlaze::BLTID; break;
380 case MBlazeCC::GE: Opc = MBlaze::BGEID; break;
381 case MBlazeCC::LE: Opc = MBlaze::BLEID; break;
404 //BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
409 TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
472 BuildMI(start, dl, TII->get(MBlaze::LWX), MI->getOperand(0).getReg())
474 .addReg(MBlaze::R0);
482 case MBlaze::SWP32:
488 case MBlaze::LAN32:
489 case MBlaze::LAX32:
490 case MBlaze::LAO32:
491 case MBlaze::LAD32:
492 case MBlaze::LAS32:
493 case MBlaze::LAA32: {
497 case MBlaze::LAA32: opcode = MBlaze::ADDIK; break;
498 case MBlaze::LAS32: opcode = MBlaze::RSUBIK; break;
499 case MBlaze::LAD32: opcode = MBlaze::AND; break;
500 case MBlaze::LAO32: opcode = MBlaze::OR; break;
501 case MBlaze::LAX32: opcode = MBlaze::XOR; break;
502 case MBlaze::LAN32: opcode = MBlaze::AND; break;
505 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
513 if (MI->getOpcode() == MBlaze::LAN32) {
515 finalReg = R.createVirtualRegister(&MBlaze::GPRRegClass);
516 BuildMI(start, dl, TII->get(MBlaze::XORI), finalReg)
523 case MBlaze::CAS32: {
533 unsigned CMP = R.createVirtualRegister(&MBlaze::GPRRegClass);
534 BuildMI(start, dl, TII->get(MBlaze::CMP), CMP)
538 BuildMI(start, dl, TII->get(MBlaze::BNEID))
548 unsigned CHK = R.createVirtualRegister(&MBlaze::GPRRegClass);
549 BuildMI(final, dl, TII->get(MBlaze::SWX))
552 .addReg(MBlaze::R0);
554 BuildMI(final, dl, TII->get(MBlaze::ADDIC), CHK)
555 .addReg(MBlaze::R0)
558 BuildMI(final, dl, TII->get(MBlaze::BNEID))
663 MBlaze::R5, MBlaze::R6, MBlaze::R7,
664 MBlaze::R8, MBlaze::R9, MBlaze::R10
699 // MBlaze does not yet support tail call optimization
702 // The MBlaze requires stack slots for arguments passed to var arg
910 RC = &MBlaze::GPRRegClass;
912 RC = &MBlaze::GPRRegClass;
974 // The last register argument that must be saved is MBlaze::R10
975 const TargetRegisterClass *RC = &MBlaze::GPRRegClass;
977 unsigned Begin = getMBlazeRegisterNumbering(MBlaze::R5);
979 unsigned End = getMBlazeRegisterNumbering(MBlaze::R10);
1039 unsigned Reg = (CallConv == CallingConv::MBLAZE_INTR) ? MBlaze::R14
1040 : MBlaze::R15;
1068 // MBlaze Inline Assembly Support
1076 // MBlaze specific constrainy
1133 return std::make_pair(0U, &MBlaze::GPRRegClass);
1140 return std::make_pair(0U, &MBlaze::GPRRegClass);
1148 // The MBlaze target isn't yet aware of offsets.
