Lines Matching defs:Const
63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
520 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
521 const TargetMachine &TM = getTargetMachine();
538 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
604 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
621 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
936 SelectionDAG &DAG) const {
980 SelectionDAG &DAG) const {
1066 SelectionDAG &DAG) const {
1094 SelectionDAG &DAG) const {
1181 SelectionDAG &DAG) const {
1241 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1242 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1290 SelectionDAG &DAG) const {
1293 const Constant *C = CP->getConstVal();
1312 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1332 SelectionDAG &DAG) const {
1335 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1345 SelectionDAG &DAG) const {
1349 const GlobalValue *GV = GA->getGlobal();
1431 SelectionDAG &DAG) const {
1435 const GlobalValue *GV = GSDN->getGlobal();
1463 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1507 const PPCSubtarget &Subtarget) const {
1513 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1615 SelectionDAG &DAG) const {
1620 SelectionDAG &DAG) const {
1663 const PPCSubtarget &Subtarget) const {
1674 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1725 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1773 static const uint16_t ArgRegs[] = {
1777 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1800 static const uint16_t ArgRegs[] = {
1805 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1824 static const uint16_t *GetFPR() {
1825 static const uint16_t FPR[] = {
1848 const SmallVectorImpl<ISD::InputArg>
1852 const {
1870 const SmallVectorImpl<ISD::InputArg>
1873 SmallVectorImpl<SDValue> &InVals) const {
1929 const TargetRegisterClass *RC;
2010 static const uint16_t GPArgRegs[] = {
2014 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2016 static const uint16_t FPArgRegs[] = {
2020 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2089 DebugLoc dl) const {
2108 bool isPPC64) const {
2130 const SmallVectorImpl<ISD::InputArg>
2133 SmallVectorImpl<SDValue> &InVals) const {
2150 static const uint16_t GPR[] = {
2155 static const uint16_t *FPR = GetFPR();
2157 static const uint16_t VR[] = {
2162 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2163 const unsigned Num_FPR_Regs = 13;
2164 const unsigned Num_VR_Regs = array_lengthof(VR);
2419 const SmallVectorImpl<ISD::InputArg>
2422 SmallVectorImpl<SDValue> &InVals) const {
2440 static const uint16_t GPR_32[] = { // 32-bit registers.
2444 static const uint16_t GPR_64[] = { // 64-bit registers.
2449 static const uint16_t *FPR = GetFPR();
2451 static const uint16_t VR[] = {
2456 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2457 const unsigned Num_FPR_Regs = 13;
2458 const unsigned Num_VR_Regs = array_lengthof( VR);
2462 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2773 const SmallVectorImpl<ISD::OutputArg>
2775 const SmallVectorImpl<SDValue> &OutVals,
2858 const SmallVectorImpl<ISD::InputArg> &Ins,
2859 SelectionDAG& DAG) const {
2921 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
3002 DebugLoc dl) const {
3099 const PPCSubtarget &PPCSubTarget) {
3267 bool isLocalCall(const SDValue &Callee)
3278 const SmallVectorImpl<ISD::InputArg> &Ins,
3280 SmallVectorImpl<SDValue> &InVals) const {
3330 const SmallVectorImpl<ISD::InputArg> &Ins,
3331 SmallVectorImpl<SDValue> &InVals) const {
3350 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3351 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3419 SmallVectorImpl<SDValue> &InVals) const {
3455 const SmallVectorImpl<ISD::OutputArg> &Outs,
3456 const SmallVectorImpl<SDValue> &OutVals,
3457 const SmallVectorImpl<ISD::InputArg> &Ins,
3459 SmallVectorImpl<SDValue> &InVals) const {
3671 DebugLoc dl) const {
3687 const SmallVectorImpl<ISD::OutputArg> &Outs,
3688 const SmallVectorImpl<SDValue> &OutVals,
3689 const SmallVectorImpl<ISD::InputArg> &Ins,
3691 SmallVectorImpl<SDValue> &InVals) const {
3752 static const uint16_t GPR[] = {
3756 static const uint16_t *FPR = GetFPR();
3758 static const uint16_t VR[] = {
3762 const unsigned NumGPRs = array_lengthof(GPR);
3763 const unsigned NumFPRs = 13;
3764 const unsigned NumVRs = array_lengthof(VR);
3821 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3823 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3858 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3859 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3879 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3880 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4058 const SmallVectorImpl<ISD::OutputArg> &Outs,
4059 const SmallVectorImpl<SDValue> &OutVals,
4060 const SmallVectorImpl<ISD::InputArg> &Ins,
4062 SmallVectorImpl<SDValue> &InVals) const {
4127 static const uint16_t GPR_32[] = { // 32-bit registers.
4131 static const uint16_t GPR_64[] = { // 64-bit registers.
4135 static const uint16_t *FPR = GetFPR();
4137 static const uint16_t VR[] = {
4141 const unsigned NumGPRs = array_lengthof(GPR_32);
4142 const unsigned NumFPRs = 13;
4143 const unsigned NumVRs = array_lengthof(VR);
4145 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4188 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4190 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4209 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4210 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4405 const SmallVectorImpl<ISD::OutputArg> &Outs,
4406 LLVMContext &Context) const {
4416 const SmallVectorImpl<ISD::OutputArg> &Outs,
4417 const SmallVectorImpl<SDValue> &OutVals,
4418 DebugLoc dl, SelectionDAG &DAG) const {
4465 const PPCSubtarget &Subtarget) const {
4497 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4521 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4548 const PPCSubtarget &Subtarget) const {
4569 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4643 DebugLoc dl) const {
4679 SelectionDAG &DAG) const {
4774 SelectionDAG &DAG) const {
4838 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4867 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4896 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4935 static const EVT VTys[] = { // canonical VT to use for each size.
4998 SelectionDAG &DAG) const {
5072 static const signed char SplatCsts[] = {
5089 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5100 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5111 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5123 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5233 SelectionDAG &DAG) const {
5398 SelectionDAG &DAG) const {
5464 SelectionDAG &DAG) const {
5481 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5542 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5590 SelectionDAG &DAG) const {
5591 const TargetMachine &TM = getTargetMachine();
5685 bool is64bit, unsigned BinOpcode) const {
5687 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5689 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5712 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5713 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5748 unsigned BinOpcode) const {
5750 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5758 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5779 const TargetRegisterClass *RC =
5780 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5781 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5877 MachineBasicBlock *BB) const {
5878 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5882 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6127 const TargetRegisterClass *RC =
6128 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6129 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6261 DAGCombinerInfo &DCI) const {
6262 const TargetMachine &TM = getTargetMachine();
6519 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6522 const SelectionDAG &DAG,
6523 unsigned Depth) const {
6560 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6588 AsmOperandInfo &info, const char *constraint) const {
6627 std::pair<unsigned, const TargetRegisterClass*>
6628 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6629 EVT VT) const {
6660 SelectionDAG &DAG) const {
6727 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6728 Type *Ty) const {
6764 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
6769 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
6774 SelectionDAG &DAG) const {
6808 SelectionDAG &DAG) const {
6835 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6855 MachineFunction &MF) const {
6864 bool *Fast) const {
6893 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
6909 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
