Lines Matching refs:Cond
210 SmallVectorImpl<MachineOperand> &Cond,
242 Cond.push_back(LastInst->getOperand(0));
243 Cond.push_back(LastInst->getOperand(1));
252 Cond.push_back(MachineOperand::CreateImm(1));
253 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
263 Cond.push_back(MachineOperand::CreateImm(0));
264 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
288 Cond.push_back(SecondLastInst->getOperand(0));
289 Cond.push_back(SecondLastInst->getOperand(1));
301 Cond.push_back(MachineOperand::CreateImm(1));
302 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
315 Cond.push_back(MachineOperand::CreateImm(0));
316 Cond.push_back(MachineOperand::CreateReg(isPPC64 ? PPC::CTR8 : PPC::CTR,
373 const SmallVectorImpl<MachineOperand> &Cond,
377 assert((Cond.size() == 2 || Cond.size() == 0) &&
384 if (Cond.empty()) // Unconditional branch
386 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
387 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
392 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
397 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
398 BuildMI(&MBB, DL, get(Cond[0].getImm() ?
403 .addImm(Cond[0].getImm()).addReg(Cond[1].getReg()).addMBB(TBB);
692 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
693 assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
694 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
695 Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
698 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
