Lines Matching refs:AMDGPU
11 /// \brief Defines an instruction selector for the AMDGPU target.
35 /// AMDGPU specific code to select AMDGPU machine instructions for
38 // Subtarget - Keep a pointer to the AMDGPU Subtarget around so that we can
85 /// \brief This pass converts a legalized DAG into a AMDGPU-specific
175 CurDAG->getTargetConstant(AMDGPU::R600_Reg128RegClassID, MVT::i32),
176 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub0, MVT::i32),
177 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub1, MVT::i32),
178 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub2, MVT::i32),
179 SDValue(), CurDAG->getTargetConstant(AMDGPU::sub3, MVT::i32)
191 return CurDAG->SelectNodeTo(N, AMDGPU::REG_SEQUENCE, N->getVTList(),
205 unsigned ImmReg = AMDGPU::ALU_LITERAL_X;
215 ImmReg = AMDGPU::ZERO;
217 ImmReg = AMDGPU::HALF;
219 ImmReg = AMDGPU::ONE;
229 ImmReg = AMDGPU::ZERO;
231 ImmReg = AMDGPU::ONE_INT;
246 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
247 // We can only use literal constants (e.g. AMDGPU::ZERO,
248 // AMDGPU::ONE, etc) in machine opcodes.
268 if (ImmReg == AMDGPU::ALU_LITERAL_X) {
319 PotentialClamp->getMachineOpcode() == AMDGPU::CLAMP_R600) {
380 if (Reg->getReg() == AMDGPU::ALU_CONST) {
392 Ops[OperandIdx[i] - 1] = CurDAG->getRegister(AMDGPU::ALU_CONST, MVT::f32);
552 return "AMDGPU DAG->DAG Pattern Instruction Selection";
560 ///==== AMDGPU Functions ====///
597 AMDGPU::ZERO, MVT::i32);
613 Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
