Lines Matching refs:AMDGPU
17 #include "AMDGPU.h"
73 case AMDGPU::PRED_X: {
81 AMDGPU::ZERO); // src1
91 case AMDGPU::BREAK: {
93 AMDGPU::PRED_SETE_INT,
94 AMDGPU::PREDICATE_BIT,
95 AMDGPU::ZERO,
96 AMDGPU::ZERO);
101 TII->get(AMDGPU::PREDICATED_BREAK))
102 .addReg(AMDGPU::PREDICATE_BIT);
107 case AMDGPU::INTERP_PAIR_XY: {
109 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
118 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W;
120 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_XY,
136 case AMDGPU::INTERP_PAIR_ZW: {
138 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
145 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y;
149 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_ZW,
165 case AMDGPU::INTERP_VEC_LOAD: {
168 unsigned PReg = AMDGPU::R600_ArrayBaseRegClass.getRegister(
173 BMI = TII->buildDefaultInstruction(MBB, I, AMDGPU::INTERP_LOAD_P0,
256 DstReg = AMDGPU::R600_TReg32RegClass.getRegister((DstBase * 4) + Chan);
265 case AMDGPU::CUBE_r600_pseudo:
266 Opcode = AMDGPU::CUBE_r600_real;
268 case AMDGPU::CUBE_eg_pseudo:
269 Opcode = AMDGPU::CUBE_eg_real;
271 case AMDGPU::DOT4_r600_pseudo:
272 Opcode = AMDGPU::DOT4_r600_real;
274 case AMDGPU::DOT4_eg_pseudo:
275 Opcode = AMDGPU::DOT4_eg_real;
